As a software engineer, you think in if statements and Boolean expressions. Hardware thinks in voltage levels and transistor switches. Let's bridge that gap.

Every digital circuit is built from two types of transistors: NMOS (conducts when gate is HIGH, pulls toward ground) and PMOS (conducts when gate is LOW, pulls toward supply). These are your atoms.

The NAND gate is king. Here's why: a 2-input NAND requires only 4 transistors — 2 PMOS in parallel (pull-up network) and 2 NMOS in series (pull-down network). Any Boolean function can be built entirely from NAND gates. This is called functional completeness, and it's why real standard cell libraries are NAND-heavy.

• NOT = 2 transistors (1 PMOS + 1 NMOS) — called an inverter
• NAND = 4 transistors — the workhorse gate
• NOR = 4 transistors — NMOS parallel, PMOS series
• AND = 6 transistors — it's a NAND followed by an inverter
• OR = 6 transistors — a NOR followed by an inverter

Notice something counterintuitive: AND and OR — the "simple" gates from your CS classes — are actually more expensive in hardware than NAND and NOR. This is because CMOS logic naturally produces inverted outputs. Getting a non-inverted output costs an extra inverter stage.

Real-world example: Inside an FPGA's look-up table (LUT), your synthesizer doesn't build discrete AND/OR gates at all. A 6-input LUT is just a 64-bit SRAM that stores the truth table directly. But in custom ASIC design — say, a CPU's arithmetic unit — gate-level choices directly affect area, speed, and power. Apple's M-series chips contain billions of these transistor-level decisions.

Rule of thumb for gate delay: A single inverter in a modern process (say 5nm) switches in roughly 5–10 picoseconds. A 2-input NAND is about 1.2–1.5× the inverter delay. Stack more transistors in series (3-input NAND, 4-input NAND) and delay grows roughly linearly with the number of series transistors, because each one adds resistance to the pull-down path. This is why synthesis tools prefer trees of 2-input gates over wide fan-in gates.

De Morgan's Law in hardware terms: NOT(A AND B) = (NOT A) OR (NOT B). This isn't just algebra — it literally describes the same circuit. A NAND gate's pull-up network (parallel PMOS) is the OR-of-inverted-inputs. The schematic proves the theorem.