This entry in Emilio Martinez's FPGA SoC series tackles something a lot of FPGA tutorials skip: the messy reality of getting a soft-core processor to drive a custom hardware block over a real bus protocol. The video walks through designing an AXI4-Stream transmitter IP in Verilog and then wiring it up so a MicroBlaze processor can kick off transfers via software.

AXI4-Stream is the workhorse interface for moving sample data through Xilinx FPGAs — DMA engines, video pipelines, DSP blocks, and SDR front-ends all speak it. But the handshake details (TVALID/TREADY, TLAST framing, backpressure) trip up newcomers constantly. Watching someone build a transmitter from scratch and then exercise it from a C program running on MicroBlaze is one of the clearest ways to internalize how the protocol actually behaves on a wire.

The "processor starts the transfer" framing is also valuable. It demonstrates the standard SoC pattern: CPU writes a control register, custom logic streams data autonomously, CPU polls or waits for completion. That mental model carries over directly to Zynq, Versal, and most ARM-based SoC FPGAs. Emilio's series-based approach (this is episode 5) suggests context-building rather than one-off demos, which is exactly what this material needs.