When you need to sample at 10 GS/s but your fastest ADC core tops out at 1.25 GS/s, you don't build a faster ADC — you build eight of them and stagger their sample instants by 1/8 of a clock period. That's a time-interleaved ADC (TI-ADC), and it's how every high-end oscilloscope and 5G/optical receiver front-end achieves double-digit gigasample rates.

The core idea: N sub-ADCs share one input signal but sample on N evenly-spaced phases of a slower clock. Sub-ADC 0 samples at t=0, sub-ADC 1 at t=T/N, sub-ADC 2 at t=2T/N, and so on. A multiplexer at the output stitches the samples back into a single stream running at N × f_sub. Each core sees a relaxed conversion window of N/f_effective, while the aggregate throughput scales linearly with N.

The three demons that ruin the trick:

• Offset mismatch — each sub-ADC has its own DC offset. The result is a fixed tone at f_s/N in the output spectrum, called an offset spur. Calibrated by measuring each sub-ADC's mean and subtracting it digitally.
• Gain mismatch — each sub-ADC has slightly different full-scale gain. This produces image tones at f_s/N ± f_in that fold your signal onto itself. Corrected by a per-channel digital gain trim.
• Timing (skew) mismatch — the sample clocks aren't perfectly N/f_s apart. This is the killer, because the error grows linearly with input frequency. A 1 ps skew on a 5 GHz sinewave is already a 1.8° phase error and a spur at roughly −40 dBc.

Rule of thumb for skew: to achieve an SFDR of X dB at input frequency f_in, your inter-channel skew must satisfy Δt < 1 / (2π · f_in · 10^(X/20)). For 60 dB SFDR at 2 GHz: Δt < 80 fs. That's why TI-ADCs live or die on their clock distribution — think H-tree with matched vias, on-chip DLL trimming per phase, and background calibration that watches the output spectrum and nudges each phase until the spurs disappear.

Real-world example: the Keysight UXR-series scope uses a 256-way time-interleaved ADC built in 20 nm CMOS to hit 256 GS/s at 10-bit resolution. Each sub-ADC runs at 1 GS/s. Background calibration continuously corrects offset, gain, and timing on every one of the 256 channels — without it, the effective number of bits would collapse from ~7 to under 4.

Why software engineers should care: the same idea shows up in SerDes receivers (interleaved samplers per lane), in multi-phase DDR data capture, and even in software when you shard a sequential workload across N workers — the coordination problem (offset/gain/skew) is structurally identical to load balancing and clock skew across distributed nodes.