When an instruction finishes executing, dependent instructions waiting in the scheduler need to fire next cycle. Not two cycles later, not three — the very next cycle. This single requirement — called back-to-back issue — shapes more of a modern CPU's physical design than almost anything else, because it forces wakeup, select, and operand-read to all happen inside one clock period.

The loop looks like this:

• Cycle N: Instruction A's result is computed in the ALU. Simultaneously, A broadcasts its destination tag across the scheduler's wakeup bus.
• Cycle N (still): Every waiting instruction's source tags are compared against the broadcast tag using CAM (content-addressable memory) cells. Matches set a "ready" bit.
• Cycle N (still): The select logic picks the oldest ready instruction(s) and grants execution slots.
• Cycle N+1: The selected instruction reads operands (often via bypass) and starts executing.

All of wakeup + select must fit in one cycle. That's the wakeup-select loop, and it is the most timing-critical path in many high-performance cores.

Why it hurts: the CAM scales badly. An N-entry scheduler with W wakeup buses needs N×W tag comparators, all switching every cycle. Intel's Skylake has ~97 scheduler entries with 8 issue ports — that's a wall of comparators burning power and limiting clock speed. Doubling the window roughly doubles wakeup delay and quadruples power.

The 2-cycle ALU compromise: some designs (early Pentium 4, some Atom variants) gave up and made the wakeup-select loop take 2 cycles. The result: a dependent add chain runs at half throughput. A loop like add rax, 1; add rax, 1; add rax, 1 executes one per cycle on Skylake but one per two cycles on a 2-cycle-loop design. That's why Intel fought tooth-and-nail to keep it at 1 cycle even as windows grew.

Speculative wakeup: for variable-latency ops (mostly loads), the scheduler wakes dependents assuming an L1 hit. If the load misses, dependents have already issued — they must be replayed. This is why load-dependent chains suffer so badly on a cache miss: it's not just the miss latency, it's the cascading replay storm.

Rule of thumb: if a dependency chain limits your throughput, count the latencies. A chain of N adds (1 cycle each) takes N cycles minimum — no amount of ROB or width helps. A chain of N imuls (3 cycles each) takes 3N. The wakeup-select loop guarantees the 1-cycle floor exists; nothing breaks it.