A DDS generates a precise, agile sine wave using only a reference clock, an adder, a register, and a lookup table. No analog VCO, no PLL loop-lock time — just a phase accumulator that spins around a circle at a programmed rate. It's what's inside every software-defined radio, function generator, and RF signal source.

The core is three pieces:

• Phase accumulator: an N-bit register (typically N=32 or 48) that adds a Frequency Tuning Word (FTW) every clock cycle. When it overflows, it wraps — which represents completing one full 2π revolution.
• Phase-to-amplitude converter: the top M bits (typically M=12–14) of the accumulator index a sine ROM. You don't need the whole accumulator width — just enough resolution to keep the amplitude quantization noise below the ADC/DAC noise floor.
• DAC: converts the sine sample to analog, followed by a reconstruction filter to smooth the staircase.

The output frequency is beautifully simple:

f_out = (FTW × f_clk) / 2^N

Concrete example: An AD9910 DDS runs at f_clk = 1 GHz with N=32. To generate 100 MHz:

FTW = (100e6 × 2^32) / 1e9 = 429,496,730 (0x1999999A)

Frequency resolution is f_clk/2^N = 1 GHz / 4.3 billion ≈ 0.233 Hz. You can hop to any of those 4 billion frequencies in a single clock — no PLL settling time.

The catch — spurs: The accumulator top bits truncate, so the phase repeats on a period shorter than 2^N unless FTW is a power of two. This creates deterministic phase-truncation spurs. The worst-case spur level (in dBc) is roughly −6.02 × M, where M is the number of ROM address bits. A 12-bit sine ROM gives ~−72 dBc spurs; 14 bits gives ~−84 dBc.

Nyquist bites hard: Output is limited to f_clk/2, and in practice you stay below ~40% of f_clk because the reconstruction filter can't have infinite rolloff. You also get images at f_clk ± f_out that must be filtered.

The clever tricks: You only store a quarter-wave (0 to π/2) in ROM — the other three quadrants come from XOR-ing address and inverting output bits. This cuts ROM size by 4×. Higher-end DDSs also use CORDIC instead of a ROM to compute sine directly, trading table area for logic depth.