The original Local APIC (xAPIC) was designed in the mid-1990s when "many cores" meant four. It used an 8-bit APIC ID field, capping the system at 256 logical processors, and exposed its registers through a memory-mapped I/O page at physical address 0xFEE00000. Both decisions became bottlenecks. x2APIC, introduced by Intel in 2008, fixed them by widening the ID to 32 bits and moving the register interface from MMIO to Model-Specific Registers (MSRs).

The MSR move matters more than it sounds. In xAPIC, writing to the Interrupt Command Register (ICR) to send an IPI meant a memory-mapped store, which had to go through the store buffer, get serialized with surrounding memory ops, and eventually reach the APIC's MMIO page. Because MMIO writes are strongly ordered on x86, the store fence semantics forced pipeline drains. In x2APIC, the same operation is a WRMSR to MSR 0x830. It's still serializing, but it's a single register write with no cache line involvement — no snoop traffic, no MMIO decode path, no page table walk for the APIC page.

The addressing change: xAPIC's ICR was split across two 32-bit MMIO registers requiring two writes (one for the target, one to trigger). x2APIC combines them into a single 64-bit MSR write. IPI latency drops from roughly ~1000 cycles to ~250 cycles on modern hardware — a 4x improvement — largely from eliminating the second serializing store.

Real-world example: A dual-socket AMD EPYC 9654 system has 2 × 96 cores × 2 threads = 384 logical processors. That's already past xAPIC's 255-usable-ID limit (ID 255 is reserved for broadcast). Without x2APIC, you literally cannot address every thread individually. This is why the Linux kernel refuses to boot with more than 255 CPUs unless x2APIC is enabled in the BIOS — check dmesg | grep x2apic and you'll see "x2apic enabled" on any modern server.

Rule of thumb: If your system has more than 255 logical CPUs, x2APIC isn't optional. If it has fewer, x2APIC still cuts IPI cost by ~4x, which matters for TLB shootdowns, scheduler wakeups, and RCU synchronization on any workload with heavy cross-core communication.

The catch: x2APIC requires interrupt remapping via the IOMMU to be enabled for external interrupts, because legacy I/O APICs still emit 8-bit destination IDs. Without remapping, MSI-X interrupts from PCIe devices can't target CPUs with IDs above 255 — the IOMMU translates the 8-bit legacy field into a 32-bit x2APIC destination on the fly.