Modern x86 CPUs have two separate mechanisms that let hot code bypass the expensive decode pipeline, and programmers routinely confuse them. The uop cache (DSB on Intel, op cache on AMD) stores decoded micro-ops keyed by instruction-pointer, holding thousands of uops across many code regions. The loop buffer (LSD — Loop Stream Detector) is smaller, holds one specific loop, and works by locking uops in the micro-op queue itself so they replay from there without even hitting the uop cache.

The distinction matters because they have different capacity limits, different triggering conditions, and fail in different ways.

• Uop cache: ~1,536–4,000 uops on recent Intel (Golden Cove: 4K), organized in sets/ways like a regular cache. Hit means you skip fetch + predecode + decode entirely. Delivers ~6–8 uops/cycle.
• LSD/Loop buffer: ~64–144 uops depending on generation. Detects that a loop fits, then gates off the fetch, decode, AND uop cache. Only the queue clocks. Big power win, and no BPU pressure on the loop branch.

Concrete example: A tight AES-CTR encrypt loop of ~40 uops running 10 million iterations. On Skylake with LSD enabled, the front-end draws almost no power for those iterations — measurable as ~5% package power reduction versus running from the uop cache. But on Skylake specifically, Intel disabled the LSD via microcode after a hyperthreading errata (SKX-102). Suddenly the same binary runs from the uop cache instead: same throughput, higher power, and now sensitive to alignment because the uop cache is 32-byte-window addressed.

Rule of thumb for when each kicks in:

• Loop ≤ ~64 uops AND no CALL/RET AND fits alignment rules → LSD (if enabled).
• Hot code up to ~4K uops with reasonable spatial locality → uop cache.
• Beyond that → legacy decode path, capped at ~4–5 uops/cycle with the complex-decoder asymmetry.

The failure mode that bites people: a loop that almost fits the LSD (say 68 uops) runs measurably slower than one at 60 uops — not because decode is slow, but because you lose the power-gated fetch and the guaranteed 6-wide delivery. Unrolling less can make loops faster. Similarly, adding a single AVX-512 instruction can push a loop past the LSD threshold and simultaneously trigger frequency throttling. Two invisible cliffs, one instruction.

The uop cache is the workhorse; the LSD is a specialized power/throughput optimization for the tightest inner loops. Knowing which one your hot code lives in tells you which knobs matter — alignment and window packing for the uop cache, uop count and instruction mix for the LSD.