A dynamic node — a wire precharged high then conditionally pulled low by an evaluation network — is only "valid" while the capacitance on the node holds its charge. The instant evaluation ends, the node is floating: no transistor is actively driving it. Leakage current, sub-threshold conduction, and gate tunneling slowly bleed charge away. At 7nm, a floating node can lose its logic-high value in microseconds. If your clock stalls (debug halt, clock gating, scan pause), the node forgets what it was and the next gate sees garbage.

The fix is a keeper latch: a tiny, weak PMOS transistor whose gate is driven by an inverter sensing the dynamic node. When the node is high, the inverter output is low, which turns the keeper PMOS on, replenishing any leaked charge from VDD. When the evaluation network pulls the node low, the inverter flips high and shuts the keeper off — but only after fighting it briefly.

The sizing problem. The keeper must be strong enough to overcome leakage but weak enough that the evaluation network can overpower it in a reasonable time. This is called contention. Rule of thumb: size the keeper PMOS such that its drive strength is 5–10× weaker than the weakest NMOS pull-down path in the evaluation network. If the eval network has stacked NMOS transistors (say, a 4-input dynamic NAND), the effective pull-down is already weakened by series stacking, so the keeper must shrink further — often to a W/L ratio under 0.1× a minimum-size device.

Real example — Intel's L1 cache wordline drivers. Dynamic decoders in high-frequency caches use precharged wordlines. During functional operation, the precharge-evaluate cycle runs at GHz rates and leakage is negligible. But when the processor enters a low-power C-state with the clock stopped mid-evaluation, leakage would corrupt the decoded address within milliseconds. Every dynamic node in the decoder path carries a half-keeper (PMOS-only) staticizer, adding ~2% area but converting the otherwise-dynamic block into a quasi-static one that survives indefinite clock stalls.

Quick calculation. A 7nm floating node has roughly 0.5 fF of capacitance and leaks ~10 nA total. Time to drop from VDD=0.75V to the inverter threshold of 0.4V: t = C·ΔV/I = (0.5e-15)(0.35)/(10e-9) ≈ 17 μs. That's why uncontrolled clock stalls of even a few hundred microseconds will silently corrupt unkeepered dynamic logic.

Keepers also defend against noise injection: a coupled aggressor wire can capacitively kick a floating node below the next-stage threshold for a few hundred picoseconds. A keeper supplies recovery current and prevents the glitch from latching downstream.