You already know H-trees: a balanced binary tree of buffers that delivers the clock to every flip-flop with matched wire lengths. H-trees work great up to about 2–3 GHz. Above that, on chips with hundreds of millions of flip-flops, the tree starts losing the skew battle. The fix at the top of the frequency curve is to throw the tree away at the last level and replace it with a clock mesh.

A mesh is exactly what it sounds like: a giant grid of wires shorted together, driven by many buffers in parallel from a shorter tree above. Every flip-flop taps the nearest mesh wire. Because the entire grid is one electrical node, all taps see essentially the same voltage transition at the same time — the mesh averages out driver mismatches, OCV (on-chip variation), and load imbalance.

Why trees fail at high frequency: In a tree, the last buffer driving each leaf is on its own. If that buffer is a slow corner and its neighbor is a fast corner, you eat the full delta as skew. In a mesh, fast drivers help charge the wire seen by slow drivers — they're literally tied together. Skew drops from ~30 ps (tree) to ~2–5 ps (mesh) on the same node.

The cost is brutal:

• Power: The mesh has enormous capacitance (often 10–20× a tree's final stage). It switches every cycle whether or not the flops underneath are toggling. Mesh power can be 20–30% of total chip power.
• Short-circuit current: Drivers fight each other during edges because their outputs aren't perfectly aligned. You burn crowbar current every transition.
• No clock gating at the leaves: The mesh is always on. Gating happens above the mesh, at coarser granularity.

Real-world example: IBM POWER and high-end Intel/AMD server CPUs use mesh distribution above ~4 GHz. The IBM POWER8 clock mesh was driven by ~1000 final-stage buffers feeding a grid covering the whole die, achieving sub-5-ps global skew at 4+ GHz. A pure H-tree at that frequency would have needed timing margin so loose the chip wouldn't have been competitive.

Rule of thumb: Mesh capacitance ≈ (die area in mm²) × (metal-stack cap density, ~0.2 pF/mm² for top metals). Mesh power = ½ × C × V² × f. For a 400 mm² die at 1V, 4 GHz: P = 0.5 × 80 pF × 1V² × 4 GHz ≈ 160 mW just to slosh the mesh — before any flop switches. That's why mesh is reserved for chips where skew, not power, is the binding constraint.

Hybrid designs are now standard: tree to a regional mesh, mesh inside each region. You get most of the skew benefit at a fraction of the power.