A 300mm silicon wafer holds hundreds or thousands of dice. Before the wafer is sawn into individual chips, every die gets tested while still part of the wafer. This is wafer probe (also called wafer sort or e-test), and it's the first electrical test a chip ever sees.

The tool is a probe card: a PCB with hundreds to tens of thousands of needle-thin tungsten or MEMS-fabricated probes arranged to match the die's bond pad layout. The wafer sits on a vacuum chuck inside a prober, which aligns the die under the probe card to micron precision, then drives the chuck upward until the probes make contact with the aluminum or copper pads. The probes leave visible "scrub marks" — small gouges that break through the native oxide to make ohmic contact.

Once contact is made, the tester runs a compressed test program: power-on checks, continuity, leakage (Iddq), scan chains, BIST, a subset of functional tests, and sometimes speed binning at multiple voltages. The full final-test suite happens later after packaging — wafer probe is about screening out the dead, not characterizing the living. A typical SoC might get 2–10 seconds of probe time per die.

Each tested die gets a bin number. Bin 1 is "fully passing." Higher bins indicate specific failure modes (Iddq fail, scan fail, slow speed bin). The wafer map is stored, and bad dice are either inked (old style) or just digitally marked. After dicing, only good dice are picked for packaging.

Known-Good-Die (KGD) testing is wafer probe taken to the extreme. For multi-chip modules, 2.5D interposers, or chiplets (think AMD's CCDs or Apple's UltraFusion), you cannot afford to assemble a $5000 package around a die that turns out to be broken. So KGD requires at-speed, full-coverage testing at the wafer level — including burn-in at the wafer ("wafer-level burn-in") — to give the same confidence a packaged part would.

Rule of thumb: If a fab yields 70% at wafer probe, and packaging+final-test yields another 95%, your overall yield is 0.70 × 0.95 ≈ 66%. Catching a defect at probe costs cents; catching it after packaging costs dollars; catching it in the field costs hundreds. This is why probe time, despite being expensive ($0.50–$2 per second of tester time), pays for itself many times over.

Real-world example: AMD's Zen chiplet strategy lives or dies on KGD. Each 8-core CCD is probed, speed-binned, and only the dice that hit the target Fmax at the target voltage get assembled into a Ryzen 9 or EPYC. Lower-binned CCDs become Ryzen 5s. The chiplet model only works because wafer probe is good enough to sort dice before they're committed to a package.