You've designed a synchronous chip. Every flip-flop needs to see the rising clock edge at the same moment. But the clock pin is one bump on the package, and the flip-flops are scattered across a 20mm × 20mm die with up to a million sinks. A wire from corner to corner has tens of picoseconds of RC delay. If one flip-flop sees the edge 200 ps before another, that 200 ps comes straight out of your timing budget — and at 2 GHz, your period is only 500 ps. Clock Tree Synthesis (CTS) is the EDA step that solves this.

The naive approach — one giant buffer driving every flip-flop — fails immediately. Fan-out of a million? Rise time would be microseconds. So you build a tree: one root buffer drives a few branch buffers, each drives more, and so on until leaf buffers drive small groups of flip-flops. Typical fan-out per stage is 4–8.

The classic geometry is the H-tree. Place the root at the chip center. Route to the midpoint of each quadrant — that's an "H" shape. From each H endpoint, route to the midpoint of its four sub-quadrants — another smaller H. Recurse. Because every path from root to leaf traverses the same total wire length, skew is geometrically zero (in theory).

In practice, skew comes from three places: unequal loading (one branch drives 17 FFs, another drives 23), OCV (on-chip variation) where two identical buffers run at slightly different speeds due to process gradients, and temperature/voltage drift across the die. Modern flows budget 50–150 ps of skew on a 3 GHz design.

Real-world example: Intel's Pentium 4 used a sector-based H-tree with deskew buffers at each leaf — small variable-delay elements that could be tuned post-silicon via fuses to compensate for measured skew. AMD Zen uses a mesh-augmented tree: an H-tree feeds a fine grid that shorts together, averaging out variation at the cost of higher power.

Rule of thumb: Clock power. The clock network typically consumes 30–40% of total dynamic power on a high-frequency CPU. That's why clock gating (covered earlier) matters so much — every gated branch saves a chunk of that budget. Estimate clock power as P = α · C · V² · f, where α ≈ 1 for ungated clocks (toggles every cycle) versus α ≈ 0.1 for data nets.

CTS tools also insert useful skew deliberately: if path A→B is tight on setup, the tool pushes B's clock later by 30 ps, stealing time from the B→C path which had slack to spare. The tree isn't just balanced — it's tuned.