Intel Processor Trace records which branches you took, but it can't tell you why the pipeline stalled. To answer that, recent Intel server parts ship Architectural Event Trace (AET) — a debug facility that streams microarchitectural events (cache fills, TLB walks, retirement stalls, uop dispatch) into a memory buffer or out the trace port, with each event timestamped against the core clock.

AET is distinct from the PMU you query with perf. The PMU counts events (e.g., "12,847 L3 misses"). AET logs every individual event with its address, latency, and the instruction pointer that caused it. You stop guessing which load missed — the trace tells you the exact RIP and the cycle it resolved.

• Event source taps: Hardware probes wired into the load-store unit, the L1/L2/L3 interfaces, the TLB walker, and the retirement unit. Each tap emits a 16-byte record when its event fires.
• Trace sink: A ring buffer in DRAM (configured via MSR IA32_AET_CTL), or routed off-chip via the Direct Connect Interface to a logic analyzer for silicon validation.
• Filtering: Per-source masks and address-range filters keep bandwidth manageable — full unfiltered AET can hit 30+ GB/s per core.
• Privilege: AET requires SGX-style attestation or platform debug authorization (closed chassis debug). It is not a Ring 0 facility — even the kernel can't enable it without a signed debug token.

Real-world example: A hyperscaler tracked an intermittent 200μs latency spike in a Redis-style KV cache. PMU counters showed elevated MEM_LOAD_RETIRED.L3_MISS during the spike, but couldn't isolate which load. With AET enabled on a debug-fused validation part, they captured 50ms of full memory-event trace around the spike and discovered a single rare load was hitting a remote NUMA node because a kernel thread had migrated the hash bucket page. Fix: mbind() the page to the local node. PMU alone would have taken weeks of guessing.

Rule of thumb for AET bandwidth: Budget ≈ 1 byte per retired uop per enabled event class. A core retiring 4 uops/cycle at 3 GHz with cache + TLB + retirement events enabled produces roughly 36 GB/s of trace data. Your DRAM ring buffer fills in microseconds — always filter by address range or sample rate, never trace unbounded.