A phase-locked loop (PLL) is a feedback system that forces a local oscillator to track the phase of a reference input. Once locked, the oscillator's output is phase-coherent with the reference — even if the reference is noisy, intermittent, or at a different frequency than the oscillator itself. PLLs are the workhorse behind frequency synthesis, clock recovery, FM demodulation, and clock multiplication inside virtually every microcontroller and SoC.

The classic PLL has four blocks in a loop:

• Phase detector (PD): Compares reference phase to feedback phase, outputs an error signal. Modern designs use a phase-frequency detector (PFD) driving a charge pump — this gives both phase and frequency discrimination, so the loop locks from any starting frequency.
• Loop filter: A low-pass filter (often a passive RC network after the charge pump) that integrates the error and rejects reference-frequency ripple. This is where loop dynamics live.
• Voltage-controlled oscillator (VCO): Generates an output frequency proportional to its control voltage. Gain is K_VCO in Hz/V (or rad/s/V).
• Feedback divider (÷N): Divides the VCO output by N before feeding back to the PD. In lock, f_out = N · f_ref.

Real-world example: integer-N frequency synthesizer. Say you want a 2.4 GHz local oscillator for a Bluetooth radio from a 10 MHz TCXO. Set N = 240, and the PLL drives the VCO until the divided output (2.4 GHz / 240 = 10 MHz) matches the reference in phase. Change N to 241, and you hop to 2.41 GHz — that's how channel hopping works. Fractional-N synthesizers use a delta-sigma modulator to dither N, achieving sub-Hz resolution at the cost of some quantization noise.

Loop bandwidth — the central design choice. Rule of thumb: set the closed-loop bandwidth to roughly f_ref/10. Wider gives faster lock and better suppression of VCO phase noise (the loop "cleans up" the VCO inside the bandwidth). Narrower gives better rejection of reference noise and spurs from the PFD. Outside the bandwidth, you see the VCO's free-running phase noise; inside, you see the reference noise multiplied by 20·log(N) dB. That 20·log(N) penalty is brutal — multiplying 10 MHz up to 2.4 GHz adds 47.6 dB of phase noise floor.

Lock time scales roughly as 1/BW. A 100 kHz loop bandwidth gives ~10–50 µs lock time, fine for frequency hopping. A 1 kHz bandwidth (used in low-spur synthesizers) needs milliseconds.

Stability: The charge pump + integrator make the loop type-II (two poles at DC). You need a zero in the loop filter — typically a series R with the integrating cap — to give 45–60° phase margin at crossover.