The asker is reading Arm's Cortex-A720 Software Optimization Guide and hits a deceptively simple sentence: in synchronous MTE mode, each store must complete its tag check before the next store executes. They want to know where in the pipeline "executed" lives — issue, retirement, or L1 arrival — and whether the second store can start speculatively.

Why it's tricky. Memory Tagging Extension checks a 4-bit allocation tag stored alongside each 16-byte granule against the logical tag in the pointer. In synchronous mode, a tag mismatch must raise a precise SError-like exception on the offending instruction — no store past the faulting one can become architecturally visible. That precision constraint is what forces the ordering the manual describes; the interesting question is what microarchitectural knobs Arm actually turns to enforce it.

The most likely reading. "Executed" here is Arm's optimization-guide shorthand for dispatched down the store pipe to the point where the tag lookup resolves, not full retirement and not L1 write. Concretely:

• Stores can still be issued out of order — the ROB doesn't stall on issue.
• But the AGU/store-address path serializes at the tag-check stage: store N+1's tag check cannot start (or at least cannot resolve) until store N's is known good. Otherwise a fault on N could be reported alongside side effects of N+1, breaking preciseness.
• Retirement of the store to the store buffer / L1 happens later and is not the gating point the guide is talking about — that's why sync mode is slower per-store but not catastrophically so.

Direction toward a solid answer. Point the asker at three sources: (1) ARM ARM section on MTE Tag Check Fault reporting modes (synchronous vs. asynchronous vs. asymmetric); (2) the A720 TRM, which describes the store pipe stages; and (3) Arm's MTE whitepaper, which explicitly contrasts sync ("precise, serialized at the store pipe") with async ("checks accumulate in TFSR, no ordering"). The gap between "architectural retirement" and "the check completes" is the crux — sync mode couples them at the tag-check stage but not at cacheline write.

Gotchas worth flagging.

• Loads behave differently: sync-mode load tag checks resolve before the load's result is forwarded, so speculative use of a mistagged load is blocked at the consumer, not by serializing the load pipe.
• Asymmetric mode (sync loads, async stores) exists precisely because store serialization is the expensive part — evidence that the store-pipe check is the bottleneck.
• Microarchitectural details differ between A720, A715, X4, etc. — the guide's wording is Arm's contract with the compiler writer, not a promise about a specific stage number.