Every ADC needs a stable input voltage during conversion. If the signal moves while the ADC is busy comparing bits, you get garbage. The sample-and-hold (S/H) circuit solves this by capturing a voltage at a precise instant and holding it steady until the next sample.

The textbook topology is dead simple: an analog switch (MOSFET or CMOS gate) feeds a hold capacitor, which is buffered by a high-impedance op-amp. When the switch closes, C_H charges to V_in. When it opens, the cap holds the voltage while the buffer presents it to the ADC.

• Track mode (switch closed): output follows input. Limited by the RC time constant of the switch on-resistance and C_H.
• Hold mode (switch open): output frozen. Voltage slowly droops due to leakage.

Choosing the hold capacitor is the central trade-off:

• Too small: droop becomes severe, and charge injection from the switch (typically 1–10 pC) creates a voltage step ΔV = Q/C_H.
• Too large: acquisition time gets long, limiting your sample rate.

Quick calculation — droop rate: If your buffer has 10 pA input bias current and your switch leaks 50 pA, total leakage is 60 pA. With C_H = 1 nF:

dV/dt = I/C = 60 pA / 1 nF = 60 µV/ms

For a 12-bit ADC on a 5 V range, 1 LSB = 1.22 mV. You'd drift one LSB in roughly 20 ms — fine for slow conversions, terrible for anything fast.

Acquisition time is set by R_on·C_H. For 12-bit accuracy you need ~9 time constants (since e⁻⁹ ≈ 0.012%). With R_on = 100 Ω and C_H = 1 nF, that's 900 ns minimum — reality dictates you also include the source impedance.

Real-world example: A digital storage scope front-end uses a fast S/H (often a Schottky diode bridge or GaAs FET switch) ahead of a flash ADC. C_H might be just 5–10 pF to get sub-nanosecond acquisition, accepting heavy droop because the ADC fires within a few nanoseconds.

Most modern SAR and pipeline ADCs have an integrated S/H on the input — but you still need to know what's happening, because the ADC datasheet specifies maximum source impedance precisely so the internal cap can charge fast enough. Drive a 12-bit SAR from a 10 kΩ source and you'll get nonsense codes. Add a unity-gain buffer (low output impedance, fast settling) and the problem disappears.

Use a C0G/NP0 ceramic or film capacitor for C_H — never X7R. Dielectric absorption in lesser ceramics causes "memory effect" where the cap slowly recovers a previous voltage, ruining accuracy.