Flip-flop-based design is rigid: data must arrive at every flop before the clock edge, or you fail timing. Slack in one stage can't help a neighboring stage that's running late. Latch-based design breaks this rule by replacing edge-triggered flops with level-sensitive latches, letting data flow through the latch during its transparent phase. This enables time borrowing (also called cycle stealing): a slow combinational path borrows time from the next stage's budget.

The trick is using two latches per pipeline stage instead of one flip-flop — typically a master latch transparent on clock low and a slave latch transparent on clock high. Data arriving late at the slave latch's input is fine as long as it arrives before the slave closes. The next stage simply starts later, and if it finishes early, the cycle balances out.

Real-world example: Intel's Pentium 4 and many of IBM's POWER processors used latch-based or pulsed-latch designs in critical paths to hit aggressive clock targets. A 4 GHz core has a 250 ps clock period — after subtracting clock skew, setup time, and jitter, you might have 180 ps of useful logic time. If one pipeline stage genuinely needs 200 ps, flip-flops fail. With latches and 20% duty-cycle borrowing, that stage can steal 50 ps from the next, which only needs 130 ps. Both stages now pass.

The math: Borrowable time equals the duration the latch is transparent, minus setup time at the closing edge. For a 50% duty cycle clock at frequency f:

• Transparent window = T/2 = 1/(2f)
• Max borrow ≈ T/2 − t_setup − t_skew
• At 2 GHz with 50 ps setup and 30 ps skew: borrow ≤ 250 − 50 − 30 = 170 ps

The catch — what makes this scary:

• Min-delay (hold) violations explode: with transparent latches, a fast path can race through two stages in one phase. You must pad short paths with buffers.
• Static timing analysis gets harder: tools must analyze every possible borrowing combination across stages, not just edge-to-edge paths.
• Debugging is miserable: a failure in stage 7 might actually be stage 5 borrowing too aggressively.
• Clock gating becomes treacherous: gating a transparent latch can leak data through unintentionally.

Modern high-performance CPUs often use pulsed latches — a compromise where a short clock pulse (say 20% of the cycle) creates a brief transparent window. You get modest time borrowing without the full hold-time nightmare of fully transparent latches.