Your ISA promises 16 or 32 architectural registers. Inside a modern out-of-order CPU, those names are a lie — there are actually 150 to 300 physical registers, and the hardware translates between them on every instruction. This translation is register renaming, and it's what lets Tomasulo's algorithm extract real parallelism instead of being strangled by name collisions.

The problem: consider R1 = R2 + R3; R1 = R4 * R5. These two instructions have no real data dependency — the second one overwrites whatever the first produced. But they both write R1, creating a WAW (write-after-write) hazard. Similarly, R3 = R1 + 1; R1 = R7 has a WAR (write-after-read) hazard: the second can't write R1 until the first reads it. These are false dependencies — artifacts of the limited register namespace, not the actual dataflow.

Renaming kills them. At decode, every destination register gets mapped to a fresh physical register from a free list. The Register Alias Table (RAT) tracks the current mapping from architectural to physical names. So R1 = R2 + R3 becomes P47 = P12 + P8; the next R1 = R4 * R5 becomes P51 = P9 * P22. Now there's no WAW — they write different physical registers. Source operands get renamed by looking up the RAT: whatever physical register currently holds the architectural source is what gets read.

The physical register file (PRF) holds all in-flight values. When an instruction commits in program order, the old physical register that used to hold that architectural name is returned to the free list. If the instruction is squashed (branch misprediction), the RAT is rolled back from a checkpoint and the speculatively-allocated physical registers are reclaimed.

Sizing rule of thumb: you need at least ROB_size + arch_register_count physical registers to avoid stalls. Skylake has 180 integer PRs to back 16 architectural names with a 224-entry ROB. Apple's M1 has ~350 integer PRs feeding a 630-entry ROB — that absurd window is only useful because renaming makes all those instructions independent enough to issue.

The cost is real: the RAT is a small CAM read every cycle for every source operand of every decoded instruction. A 4-wide decoder doing 3 sources per instruction needs 12 RAT reads per cycle, plus 4 writes for destinations. This is one of the hottest structures on the chip, and it's why front-end width is so expensive — renaming bandwidth scales superlinearly with issue width.