Single-ended signaling — one wire referenced to ground — works fine at low speeds. But push past a few hundred MHz and the wire becomes an antenna: it radiates EMI, picks up noise, and the ground reference shifts as currents flow elsewhere on the PCB. Differential signaling solves all three problems by sending the signal on two wires carrying opposite polarities, and the receiver looks only at the difference between them.

How it works: The transmitter drives D+ high and D− low for logic 1, and the reverse for logic 0. The receiver is a comparator: if (D+) − (D−) > 0, output 1, else 0. Any noise that couples onto both wires equally — called common-mode noise — gets subtracted out. A 500 mV ground bounce that would corrupt a single-ended signal is invisible to a differential pair.

LVDS (Low-Voltage Differential Signaling) is the workhorse standard. The transmitter is a current-mode driver pushing ~3.5 mA through a 100 Ω termination resistor at the receiver, producing a swing of only 350 mV centered around a 1.2 V common-mode voltage. Small swing means fast edges and low power — an LVDS pair burns about 35 mW versus hundreds for equivalent CMOS.

Real-world example: the LVDS interface inside your laptop lid. The GPU sends pixel data over four LVDS pairs running at ~945 Mbps each to the LCD panel. Without differential signaling, the flexible cable through the hinge — bending, flexing, picking up Wi-Fi radiation — would garble the image. With LVDS, you get a clean display even as the cable wears.

The PCB rules that matter:

• Length matching: the two wires of a pair must be within ~5 mil (0.13 mm) of each other, or skew between D+ and D− creates timing errors. At 1 Gbps, one bit is ~1 ns wide; 50 ps of skew is already 5% of your eye.
• 100 Ω differential impedance: set by trace width and spacing on the stackup. Mismatched impedance causes reflections that close the eye diagram.
• Tight coupling: keep the two traces close (typically 2× trace width apart) so external noise couples equally to both.

Rule of thumb for skew budget: allowable intra-pair skew ≈ 10% of the unit interval. At 2.5 Gbps (UI = 400 ps), that's 40 ps — about 6 mm of FR-4 trace, since signals travel ~150 ps/inch. Miss that and your bit error rate spikes.

LVDS spawned descendants — PCIe, SATA, HDMI, USB 3, DisplayPort, MIPI — all use differential pairs with similar physics, just faster edges, embedded clocks (8b/10b or 128b/132b), and pre-emphasis to compensate for channel loss.