When one MOSFET can't handle the current, engineers reach for the obvious solution: put two (or four, or eight) in parallel. Unlike BJTs, MOSFETs have a positive temperature coefficient of R_DS(on) — as a device heats up, its channel resistance rises, forcing current to divert to cooler siblings. This is often described as "self-balancing," and it's used to justify skipping ballast resistors entirely. That's only half the story.

The self-balancing behavior only applies in the fully-enhanced (ohmic) region, where R_DS(on) dominates. During switching transitions, MOSFETs briefly operate in saturation, where drain current is set by V_GS − V_GS(th). Here the temperature coefficient of V_GS(th) is negative — a hotter device turns on harder, hogging more current, heating faster, and running away thermally. The result: one FET switches almost all the current for tens of nanoseconds every cycle, while its siblings loaf.

Three failure modes you'll actually see:

• V_GS(th) mismatch — datasheets typically spec 2–4 V range. The lowest-threshold device turns on first and off last, absorbing the switching losses.
• Gate drive layout asymmetry — unequal gate trace lengths create different R_G·C_iss time constants. The FET closer to the driver switches first.
• Common source inductance — shared source-return inductance between paralleled FETs causes oscillation and unequal V_GS during transitions.

Practical mitigations:

• Use individual gate resistors (typically 4.7–22 Ω) at each MOSFET gate, not a single shared one. This damps parasitic oscillation between paralleled devices and decouples their gates.
• Buy MOSFETs from the same date code / reel — parametric matching within a lot is usually far tighter than the datasheet spread.
• Enforce symmetric layout: mirror-image gate traces, shared Kelvin source return, identical drain-to-load paths.
• Derate hard: with N FETs in parallel, don't count on N× current — plan for 0.7·N× at worst.

Real-world example: A 48 V, 100 A synchronous buck converter uses four IPP083N10N5 MOSFETs (100 V, 8.3 mΩ) in parallel for the low-side switch. Without individual 10 Ω gate resistors, ring frequencies around 40–80 MHz between the four gates caused one FET to see 3 V of overshoot on V_GS — degrading its threshold over thousands of hours until it started hogging current and eventually failed short.

Rule of thumb: Switching loss per device scales with the ratio of its own V_GS(th) to the group minimum. A 200 mV threshold spread in a hard-switched application means the low-threshold FET dissipates roughly 1.5–2× the switching energy of its siblings. Static R_DS(on) sharing may look balanced on a DMM — the failures happen during the nanoseconds you can't measure.