You write add rax, rbx and the CPU sees... something completely different. The architectural register rax is a fiction — a name. The actual bits live in a physical register file with 180+ entries (Intel Golden Cove has 280 integer PRF entries). The rename map (also called the Register Alias Table, or RAT) is the dictionary that translates between these two worlds, and it sits squarely in the critical path of every instruction.

The rename map is a small SRAM table indexed by architectural register number, where each entry stores the physical register number currently holding that logical register's value. On x86-64, you have 16 GPRs, so the integer RAT has 16 entries. Each entry might hold a 9-bit physical register ID (for a 512-entry PRF).

How it works each cycle:

• Source lookup: For each instruction being renamed, read the RAT entries for its source architectural registers. This gives the physical register tags the instruction will wait for in the scheduler.
• Destination allocation: Pop a free physical register from the free list, write it into the RAT entry for the destination architectural register, overwriting whatever was there.
• The old mapping doesn't vanish — it's saved in the ROB entry so it can be reclaimed when the instruction retires (or restored on a misprediction).

The hard part is parallelism. Renaming 6 instructions per cycle means you need 12 read ports (2 sources each) and 6 write ports on this tiny table. Worse, if instruction 2 reads what instruction 1 just wrote, you need intra-bundle dependency checking — comparators between every pair of instructions in the rename bundle, with bypass muxes that forward the new mapping instead of reading the stale RAT value.

Concrete example. Consider:

mov rax, [rdi]    ; renames rax → P47
add rax, 1        ; reads rax → P47, writes rax → P51
mov [rsi], rax    ; reads rax → P51

All three instructions rename in one cycle. The third instruction must see P51 (just allocated this cycle), not whatever the RAT held at cycle start. The bypass network handles this — at a transistor cost that grows quadratically with rename width. This is one reason rename width caps around 6–8 on real silicon.

Rule of thumb: Rename bypass complexity scales as O(W²) where W is the rename width. Doubling rename width quadruples the comparator count and roughly doubles the cycle time of that stage — the reason 4-wide rename held for years before Intel and AMD pushed to 6.

On a branch misprediction, the RAT must be rolled back. Two strategies exist: checkpoint the entire RAT at every branch (fast recovery, expensive storage), or walk the ROB backward restoring old mappings (cheap storage, slow recovery). Modern designs typically checkpoint at low-confidence branches and walk for the rest.