Out-of-order CPUs want to execute loads as early as possible — a load that misses to DRAM costs 300 cycles, so waiting for older stores to resolve is catastrophic. But loads cannot blindly skip stores: if an older store writes address X and a younger load reads X, the load must see the store's value, not whatever was in cache. The load-store queue (LSQ) is the hardware that lets loads execute speculatively while guaranteeing correctness.

The LSQ is actually two structures working together: a store queue (SQ) holding in-flight stores with their addresses, data, and program order, and a load queue (LQ) holding in-flight loads with their addresses and the data they returned. Stores sit in the SQ until they retire — only then do they write to cache. Loads check the SQ on dispatch via a content-addressable memory (CAM) lookup on the address.

Three cases when a load executes:

• No older store to the same address: load reads from cache normally.
• Older store with matching address and ready data: store-to-load forwarding — the SQ bypasses the value directly into the load's destination register, no cache access needed. This is why modern CPUs can hit ~4-cycle store-to-load latency.
• Older store with unknown address (address not computed yet): the load speculates that there's no conflict and executes anyway.

That third case is where it gets spicy. When the older store's address finally resolves, hardware does a reverse CAM lookup against the LQ: did any younger load that already executed read this address? If yes — memory order violation. The pipeline flushes the load and everything after it, costing 15-20 cycles. This is called a memory disambiguation misprediction.

Real-world example: Intel's Nehalem (2008) added a memory disambiguation predictor that learns which loads historically conflict with prior stores. Aggressive loads execute early; risky ones stall. Intel claimed ~40% reduction in load latency on memcpy-style workloads where the compiler couldn't prove non-aliasing. AMD's Zen has a similar predictor with a small history table indexed by load PC.

Rule of thumb: SQ depth is roughly peak_store_throughput × retire_latency. A CPU retiring 1 store/cycle with 40-cycle ROB depth needs ~40 SQ entries. Skylake has 56 SQ / 72 LQ entries; Apple's M1 famously has ~150+ LQ entries, enabling its absurd memory-level parallelism. Each entry costs area (CAM cells are ~10× SRAM) and power, so depth is a deliberate trade against IPC gains.