2026-05-09
A PLL needs to compare a reference clock against a feedback clock and produce an error signal. The naive approach — an XOR gate — works, but it has a fatal flaw: it only compares phase, not frequency. If the feedback clock is running at twice the reference rate, an XOR detector happily reports "locked" because the average duty cycle still looks balanced. The PLL never converges. The phase-frequency detector (PFD) fixes this by tracking which edge arrived first and how long ago.
The classic PFD is built from two D flip-flops and one AND gate. Both flip-flops have their D inputs tied high. The reference clock clocks one flip-flop (producing UP), the feedback clock clocks the other (producing DOWN). When both UP and DOWN go high simultaneously, the AND gate asynchronously resets both flip-flops. That's the entire circuit — about 20 transistors.
The behavior falls out of the structure:
That third behavior is the magic. A PFD has an infinite capture range in theory — it will pull the VCO toward the right frequency from any starting point, unlike an XOR detector which only locks within ±90° of phase. The output drives a charge pump that pushes current into a loop filter capacitor, integrating the error into a control voltage.
Real-world example: Every Ethernet PHY, every DDR memory controller, every CPU clock multiplier uses a PFD. When your laptop wakes from sleep and the 100 MHz reference crystal needs to spin up a 4.2 GHz CPU clock, the PFD is what guarantees the multiplier locks rather than landing at some harmonic.
Rule of thumb: PFD dead zone is the tiny phase error where neither flip-flop produces a usable pulse — typically 50-200 ps. To eliminate it, designers add a deliberate reset delay so both UP and DOWN always pulse briefly, even at zero error. Lock jitter is roughly dead_zone / VCO_gain — a 100 ps dead zone with a 200 MHz/V VCO yields ~20 ppm of residual jitter.