You already know combinational hazards exist — a logic output can momentarily glitch when inputs transition, even when both the start and end states agree the output shouldn't change. The follow-up question is: how do synthesis tools actually find and eliminate those hazards before tapeout? The answer is a formal procedure built on prime implicants and Boolean cube covering.

A static 1-hazard occurs when output should stay at 1, but a single input transition causes a momentary 0. Geometrically: two minterms that are adjacent on the Karnaugh map (differ in one variable) are covered by different product terms, with no overlapping cube bridging them. As the input flips, the first AND gate turns off before the second turns on — and the OR briefly sees all zeros.

The fix: add a redundant prime implicant that covers the transition boundary. The resulting cover is called a complete sum — every pair of adjacent minterms in the ON-set is covered by at least one common cube. Synthesis tools call this hazard-free two-level minimization.

Concrete example. F(A,B,C) = A'B + AC. ON-set: {010, 011, 101, 111}. Consider transition 011 → 111 (A flips 0→1, B and C stable). At 011, A'B=1, AC=0, F=1. At 111, A'B=0, AC=1, F=1. Mid-transition, with A in between, both products can be 0 → output glitches to 0. Adding BC (which covers both 011 and 111) eliminates the hazard: F = A'B + AC + BC. The extra term is logically redundant but topologically essential.

Dynamic hazards are worse — output transitions multiple times when it should transition once. They appear in multi-level logic where one input fans out through paths of different depths. Detection requires path sensitization analysis: trace every signal path from a transitioning input to the output and check if more than one path is simultaneously sensitized with opposing polarities.

Rule of thumb for synthesis: if your downstream logic is edge-triggered (samples on a clock edge after combinational settling), hazards don't matter — STA's setup-time check absorbs them. If downstream logic is level-sensitive (latches, asynchronous resets, clock-gating enables, async FIFO pointers), every hazard is a potential bug. Synthesis tools like Synopsys DC accept set_hazard_free attributes on those specific nets and add redundant cubes only where needed.

Real-world bite: a clock-gating enable computed as en = sel ? a : b with a glitchy sel can produce a runt clock pulse downstream, corrupting hundreds of flip-flops simultaneously — the exact reason ICG cells require glitch-free enables and CAD tools refuse to gate clocks with hazard-prone logic.