Modern x86 CPUs have a deep impedance mismatch between fetch/decode and execution. The front-end fetches 16-32 bytes of variable-length instructions per cycle and decodes them into fixed-width µops. The back-end consumes µops at a rate dictated by scheduling, port pressure, and memory stalls. These rarely match cycle-to-cycle. The micro-op queue (also called the IDQ — Instruction Decode Queue) is the elastic buffer between them.

On Intel Skylake-derived cores, the IDQ holds 64 µops per thread (128 total with SMT). It accepts µops from three sources: the legacy decoders (up to 5 µops/cycle), the µop cache (up to 6 µops/cycle), and the microcode sequencer (4 µops/cycle for complex instructions like CPUID or string ops). It feeds the renamer at up to 6 µops/cycle on Sunny Cove and later.

Why does an elastic buffer matter? Three reasons:

• Decoupling stalls: If the back-end stalls on an L3 miss, the front-end keeps decoding into the IDQ. When execution resumes, those µops are ready instantly — no decode latency on the critical path.
• Smoothing bursts: The µop cache can deliver 6 µops in one cycle, then 0 the next when the line boundary hits. The IDQ smooths this into steady issue to the renamer.
• Loop Stream Detector hand-off: When the LSD detects a loop that fits entirely in the IDQ (≤64 µops, no calls/returns), it locks the queue and replays µops from it, shutting down fetch and decode entirely. This is a major power win for tight inner loops.

Real-world example: A matrix multiplication kernel with a 40-µop inner loop runs out of the LSD on Skylake. The front-end clock-gates the decoders and µop cache, dropping front-end power by ~30%. Unroll that loop to 80 µops and you lose LSD eligibility — the µop cache fires every cycle instead, and your perf/watt drops measurably even though IPC is unchanged.

Rule of thumb: If your hot loop body decodes to under 64 µops, the LSD will run it. Check with perf stat -e idq.dsb_uops,idq.mite_uops,lsd.uops — if lsd.uops dominates, you're in the sweet spot. Roughly: 1 x86 instruction ≈ 1.1 µops for typical integer code, so ~55 instructions fits.

AMD Zen calls its equivalent the Op Queue, holds 72 µops, and similarly powers down upstream stages when running from it. The principle is universal: any time two pipeline domains run at different rates, you need a queue to absorb the variance, or you pay the cost of the slower one on every cycle.