Static CMOS gates are robust but slow and area-hungry — every input drives both an NMOS pull-down and a PMOS pull-up. A 4-input NAND needs 8 transistors and the PMOS stack is painfully slow because holes have ~2.5× lower mobility than electrons. Dynamic logic throws out the PMOS network and replaces it with a single precharge transistor clocked by φ.

The recipe in two phases:

• Precharge (φ=0): A single PMOS turns on, charging the output node to VDD. The NMOS evaluation network is disconnected from ground by a "foot" NMOS.
• Evaluate (φ=1): The precharge PMOS turns off, the foot NMOS turns on. If the inputs make a conducting path through the NMOS network, the output discharges to 0. Otherwise it stays high — held there by parasitic capacitance.

A 4-input dynamic NAND uses 6 transistors (4 NMOS in series + precharge + foot) instead of 8, and the slow PMOS stack is gone entirely. You get roughly 2× the speed at ~75% the area.

The catch: dynamic outputs are valid only briefly. You cannot cascade dynamic gates directly — if gate B evaluates while gate A is still precharging high, B sees a transient '1' and may discharge incorrectly. The fix is domino logic: place a static inverter after every dynamic gate. The inverter output is low during precharge, so the next dynamic gate sees '0' (non-conducting) and stays precharged. When evaluation starts, '1's "fall like dominoes" down the chain.

Real-world example: Intel's Pentium 4 used domino logic extensively in its integer ALU to hit 3+ GHz in 2001. The 64-bit carry-lookahead adder ran at half the cycle time using domino, while the static-CMOS version couldn't meet timing. Modern processors still use domino for register file decoders and tag-compare logic in caches.

Charge-sharing rule of thumb: The dynamic node holds charge Q = C_out × VDD. If an internal node in the NMOS stack has capacitance C_int that was at 0V, when it shares charge the output droops to VDD × C_out/(C_out + C_int). Keep C_int < 0.1 × C_out or insert keeper PMOS transistors to refresh the high level — otherwise leakage and charge-sharing flip your output within microseconds.

Dynamic logic is also monotonic: outputs can only fall during evaluation, never rise. That rules out direct inversion in the NMOS network, which is why every domino stage needs that trailing inverter.