DDR3 routing is one of those PCB design topics that separates hobbyist layout work from professional high-speed digital design. It's notoriously fussy: you're dealing with tight timing budgets, length-matched groups, controlled impedance, fly-by topology, and termination schemes that all have to work together or the memory bus simply won't train.

This video zeroes in on the address, command, and control (ACC) group specifically — the signals that clock data into DRAM chips via a fly-by daisy chain rather than the point-to-point routing used for data lanes. Understanding why ACC uses fly-by (and why DQ/DQS don't) is a core concept that a lot of tutorials skip.

PajoPCB tends to work from actual layouts rather than whiteboard theory, which is what makes the channel useful. You get to see real trace routing decisions: how to sequence the DRAM chips along the bus, where to place the VTT termination, how to handle length matching against the clock pair (DDR3_CK), and the trade-offs when your board space is constrained.

If you've done basic two-layer PCBs and want to level up to memory interfaces on multi-layer stackups — or if you're staring at a DDR3 datasheet wondering how the timing constraints translate into actual copper — this is a directly applicable walkthrough from someone who does this professionally.