A textbook Miller integrator (op-amp, input resistor R, feedback capacitor C) has a nasty real-world problem: it always drifts. Op-amp input bias current and input offset voltage both act like tiny DC signals at the summing junction, and the integrator dutifully integrates them. Even a "good" JFET-input op-amp with 10 pA bias current will ramp the output of a 1 nF integrator at 10 mV per second. Leave it running for a minute and you're railed.

The fix is a reset switch across the integration capacitor. When closed, it forces V_C = 0 (or whatever offset the summing junction wants), zeroing the integrator state. When opened, integration resumes from a known starting point. This is fundamental to dual-slope ADCs, charge-balancing electrometers, sample-and-hold front-ends, and analog compute blocks.

Switch technology matters enormously:

• JFET switches (e.g., 2N4391): low charge injection but limited voltage range.
• CMOS analog switches (e.g., ADG419, DG419): easy to drive but inject charge (~1–20 pC) when opening, dumping a step voltage ΔV = Q_inj/C onto your integrator output.
• Reed relays: near-zero charge injection and femtoamp leakage, but slow (~1 ms) and mechanically finite.
• Photo-MOS relays: no bounce, low leakage, isolated drive — increasingly the default for precision reset.

Real-world example: In a dual-slope integrating DMM, the integrator runs up during a fixed integration time T_int from the input, then ramps down against a reference. Between measurements, the reset switch must fully discharge C before the next cycle — residual charge shows up as an offset in the next reading. High-end 6½-digit meters typically use two switches (reset plus a second one during the auto-zero phase) to null out both the integrator offset and the comparator offset.

Charge injection rule of thumb: If your CMOS switch spec sheet lists Q_inj = 4 pC and your integrator capacitor is C = 10 nF, the reset-opening step is ΔV = 4 pC / 10 nF = 0.4 mV. For a 10 V full-scale integrator that's 40 ppm error — fine for 12-bit work, catastrophic for 20-bit. Two mitigations: use a larger C (trade drift for injection), or use a dummy switch — a second, unused switch driven with the complementary clock, whose channel charge cancels the reset switch's injection to first order.

Also watch the switch's OFF leakage. A 1 nA leak into a 1 nF cap drifts 1 V/s — your reset switch can become the very drift source you were trying to fix.