Every EEPROM, flash chip, and microcontroller with non-volatile memory stores bits by trapping electrons on an electrically isolated conductor called a floating gate. Understanding the analog physics beneath the "just write to address 0x100" abstraction explains why flash wears out, why programming needs high voltages, and why your MCU's EEPROM emulation is so slow.

A floating gate MOSFET has two stacked gates: a control gate on top (like a normal MOSFET gate) and a floating gate underneath, completely surrounded by SiO₂ dielectric maybe 8–10 nm thick. Charge placed on the floating gate has nowhere to go — the oxide is such a good insulator that electrons stay put for 10+ years at room temperature. That trapped charge shifts the transistor's threshold voltage (Vt), and a read circuit senses whether it conducts at a reference gate voltage.

Getting electrons onto the gate requires punching them through the oxide via Fowler-Nordheim (F-N) tunneling. Apply roughly 10–20 V across the thin oxide (creating fields of ~10 MV/cm) and quantum mechanics takes over: electrons tunnel through the triangular energy barrier. Current density follows J = A·E²·exp(-B/E), exponentially sensitive to field strength. Double the field, and tunneling current jumps orders of magnitude.

Concrete example: a typical NOR flash cell might have Vt ≈ 1 V when erased (gate uncharged, transistor conducts at low Vgs) and Vt ≈ 5 V when programmed (electrons trapped, needs higher Vgs to turn on). Read at Vgs = 3 V: erased cells conduct (logic 1), programmed cells don't (logic 0). To program, the chip's internal charge pump generates ~18 V from a 3.3 V supply — this is why external EEPROMs need no programming voltage pin anymore, but also why writes are slow (milliseconds vs. nanoseconds for reads).

Wear-out mechanism: every tunneling event slightly damages the oxide, creating trap sites that snag electrons permanently. Over 10⁴–10⁵ cycles (consumer flash) or 10⁶ cycles (industrial EEPROM), Vt shift becomes unreliable and the cell fails. This is why wear leveling exists in SSDs and why you never put a write-heavy log in a fixed MCU EEPROM address.

Rule of thumb: to estimate flash endurance for a logging application, divide rated endurance cycles by writes-per-day. A 100k-cycle EEPROM byte written every 10 seconds burns out in about 100,000 / 8,640 ≈ 11 days. Spread writes across 256 addresses and you get 8 years. Wear leveling isn't optional for anything logging faster than once per minute.

Erase is the inverse: reverse the field to pull electrons off. NAND flash erases in large blocks because it's faster to share erase circuitry across thousands of cells than to route it per-byte.