At nanometer geometries, the wire between two gates often delays your signal more than the gates themselves. Every metal trace on a chip has resistance (because copper isn't a perfect conductor) and capacitance (because it sits next to other wires and the substrate). Together they form a distributed RC network that low-pass filters your edge.

The classic model is the Elmore delay: for a wire of length L with per-unit resistance r and per-unit capacitance c, the delay to the far end is approximately 0.5 · r · c · L². The L² is what kills you — doubling wire length quadruples delay. This is why long global signals (clocks, resets, bus enables) get buffered every few millimeters instead of being run as one long trace.

A concrete number: In a 7nm process, a typical M3 metal wire has r ≈ 200 Ω/mm and c ≈ 200 fF/mm. A 1mm unbuffered wire then has Elmore delay ≈ 0.5 × 200 × 200×10⁻¹⁵ × 1² = 20 ps. That sounds tiny — until you realize a gate in the same process switches in 5 ps. The wire is 4× slower than the logic it's connecting.

The rule of thumb: Insert a buffer when wire delay exceeds the delay of two inverters. Optimal buffer insertion spaces repeaters so that segment delay equals buffer delay — this converts the L² curve into a linear delay-vs-length line. Modern place-and-route tools do this automatically during a step called buffer insertion or repeater planning.

Wire load models matter even before layout exists. During synthesis, the tool has no idea how long wires will be, so it uses a statistical wire load model — a lookup table that estimates capacitance based on fanout and block size. These are notoriously optimistic for large blocks, which is why pre-layout timing reports often look great and post-layout reports look terrible. The fix in modern flows is physical synthesis: the synthesizer does a rough placement so it can estimate real wire lengths.

Wire capacitance also creates coupling between adjacent traces. A switching aggressor can inject noise onto a quiet victim wire — up to 30% of VDD in dense routing. Tools mitigate this by spacing critical nets, shielding with grounded wires, or routing them on different layers.

The takeaway for designers: at advanced nodes, RTL changes that "shouldn't matter" — moving a register across a block boundary, increasing fanout from 4 to 16 — can blow your timing not because of added logic, but because of added wire.