When you need both high resolution (12-16 bits) and high speed (tens to hundreds of MSPS), neither SAR nor delta-sigma will do. SAR runs out of speed past ~10 MSPS at 16 bits; delta-sigma trades bandwidth for resolution. The pipelined ADC solves this by breaking the conversion into stages that work concurrently on different samples — like an assembly line.

How the pipeline works: Each stage resolves a few bits (typically 1.5 to 4 bits per stage), then passes a "residue" to the next stage. A single stage contains:

• A sample-and-hold to freeze the input
• A small flash ADC (a few comparators) to resolve a coarse digital code
• A DAC that reconstructs the analog equivalent of that coarse code
• A subtractor that produces the residue (input minus DAC output)
• A gain amplifier (usually 2× or 4×) that scales the residue back to full-scale for the next stage

The "MDAC" (multiplying DAC) often combines the last three functions into one switched-capacitor op-amp block. Because every stage processes a different sample simultaneously, the throughput equals the clock rate — but the latency is N clock cycles for N stages. That latency is why pipelined ADCs are unsuitable for control loops but excellent for streaming applications.

Digital error correction: The trick that makes pipelines practical is overlapping bit ranges between stages. Each stage resolves 1.5 effective bits using 3 comparator levels — the extra "half bit" of redundancy lets the next stage correct comparator offset errors in the current stage. Without this, comparator offsets of even a few mV would destroy linearity.

Real-world example: The AD9252 is an 8-channel, 14-bit, 50 MSPS pipelined ADC commonly used in medical ultrasound imaging. Ultrasound transducers produce wideband signals (1-15 MHz) requiring 60+ dB SNR — perfectly matched to pipeline strengths. SDR receivers and digital oscilloscopes also rely heavily on pipelines.

Rule of thumb — stage count: For an N-bit pipeline with B bits per stage (with 0.5-bit overlap), you need roughly N / (B − 0.5) stages. A 14-bit ADC with 1.5-bit stages needs ~14 stages; with 3.5-bit stages, only ~5. More bits per stage means fewer stages (lower latency, less power) but tighter comparator accuracy and a more demanding MDAC gain.

Critical design issue: The first stage dominates noise and linearity — its errors propagate through every subsequent gain stage. Designers spend most of their effort here, often using a beefier op-amp and larger sampling caps (kT/C noise scales with 1/C).