When software ships, it runs on the silicon you bought. When silicon ships, it runs on every silicon that came off the wafer — and each die is slightly different. Static Timing Analysis (STA) corners are how hardware engineers prove the chip works across the full range of manufacturing variation, voltage, and temperature — without simulating a single test vector.

The three axes of variation (PVT):

• Process (P): Transistors come out faster or slower than nominal depending on doping, lithography, and etch. Labeled SS (slow-slow), TT (typical), FF (fast-fast), plus skewed corners SF and FS where NMOS and PMOS go opposite directions.
• Voltage (V): Vdd droops under load and rises when idle. A 1.0V nominal rail might be specified at 0.9V–1.1V.
• Temperature (T): Junction temp swings from −40°C (automotive cold start) to +125°C (datacenter hotspot). Counterintuitively, at low Vdd, cold transistors can be slower than hot ones — "temperature inversion."

The two failures you check at opposite corners:

• Setup violations happen when logic is too slow. Check at the slow corner: SS process, low Vdd, high temp (or cold, if inverted). Worst-case data arrival vs. earliest clock capture.
• Hold violations happen when logic is too fast — data races through and corrupts the next flop before the clock edge captures the old value. Check at the fast corner: FF process, high Vdd, low temp.

Real example: A 7nm SoC at TSMC typically signs off at ~9 corners: {SS, TT, FF, SF, FS} × {min Vdd, max Vdd} × {−40°C, 0°C, 125°C}, often pruned to the dominant ones per analysis type. Multiply by RC corners (Cmax/Cmin/RCmax/RCmin for interconnect variation) and you get 30+ corner combinations. Each one is a full STA run on hundreds of millions of timing paths.

Rule of thumb — derate the clock: If your nominal cycle is 1.0 ns, plan for usable timing budget around 0.7–0.8 ns after subtracting clock uncertainty (jitter + skew, ~5–10% of period), OCV (on-chip variation) derate (~3–5%), and margin for crosstalk and aging (~5%). The "1 GHz chip" is really a "1.25 GHz design clocked at 1 GHz so it still works on the worst die at 125°C three years from now."

Why this matters: A path that passes at TT by 50 ps may fail SS by 80 ps. Signing off only at typical is how you get a chip that works on the bench and dies in the field.