When a floating-point adder subtracts two close numbers — say, 1.0000001 − 1.0000000 — the result is tiny and the mantissa has a long run of leading zeros. To get back into IEEE 754 normal form, hardware must shift left until the leading bit is 1, then adjust the exponent. The naive approach: wait for the adder to finish, count the zeros with a Leading Zero Detector (LZD), then shift. That's three serial stages on the critical path.

A Leading Zero Anticipator computes the shift amount in parallel with the addition itself. It looks at the input operands — not the sum — and predicts where the leading 1 of the result will be, with an error of at most ±1 bit.

How the prediction works. For each bit position, the LZA generates a per-bit signal from the two operands A and B (and their alignments). A common encoding classifies each column as:

• Z (zero): both bits agree and produce no carry out — the result column will be 0 unless a carry rolls in.
• P (propagate): bits differ — result column depends on incoming carry.
• G (generate): both bits force a 1 out.

The LZA scans this string for the leftmost transition pattern (typically Z…ZP or G…GP) that marks where the first 1 of the difference must appear. A priority encoder turns that position into a shift count, which feeds a barrel shifter — all while the actual adder is still resolving carries.

The ±1 error problem. Because the LZA doesn't see the carry-out of the full add, it can be off by one bit. Hardware handles this two ways: (1) shift by the predicted amount, then check the top bit and do a single 1-bit correction shift; or (2) build a correction-free LZA using more complex encoding that tracks borrow patterns exactly — costlier in area but no second shift.

Concrete example. Intel's Pentium 4 FPU and IBM's POWER floating-point units both used LZAs to keep the FP add latency at 3–4 cycles instead of 5–6. For a 53-bit double-precision mantissa, eliminating one full shifter-stage from the critical path can save 300–500 ps at GHz frequencies — often the difference between hitting your target Fmax or not.

Rule of thumb: An n-bit LZA tree has depth ≈ log₂(n) — same as a carry-lookahead adder — so the prediction finishes at roughly the same time as the sum. Without it, normalization is serial and the FP adder is one stage slower for every pipeline you build.