A basic PLL locks its output at an integer multiple N of the reference: if the reference is 10 MHz and N=245, the output is 2450 MHz. Fine — until you need 2450.5 MHz. You can't get there by picking a new integer, and dropping the reference to 5 MHz to gain resolution destroys loop bandwidth and phase noise. Fractional-N synthesis is the trick: make N change over time so the average divide ratio is non-integer.

The naïve approach — divide by 245 half the time and 246 the other half to get an average of 245.5 — works, but the periodic switching creates massive fractional spurs. The phase detector sees a repeating error pattern at the switching frequency, and that pattern modulates the VCO. You get discrete tones offset from the carrier by kHz, which is fatal for RF and bad even for CPU clocks.

The solution is a delta-sigma modulator driving the divider select. Instead of a periodic pattern, the DSM produces a pseudo-random sequence of integers whose running average equals the desired fraction. A first-order DSM outputs mostly 245s with an occasional 246 to make up the deficit; a MASH 1-1-1 (three cascaded first-order stages) shapes the quantization error so it's pushed to high frequencies where the PLL loop filter attenuates it. The average is exact; the noise is out of band.

Worked example. You want 2450.5 MHz from a 10 MHz reference. Set N.frac = 245 + 0.05. Every reference cycle, the DSM chooses 245 or 246 such that after 20 cycles it's produced exactly one 246 and nineteen 245s. Average = (19·245 + 246)/20 = 245.05. Multiply by 10 MHz: 2450.5 MHz. The switching happens at ~500 kHz, but a MASH-3 shapes that noise up to megahertz, where a loop filter with 100 kHz bandwidth kills it.

Rule of thumb: loop bandwidth ≤ f_ref / 10 for stability. Loop bandwidth ≤ 1/20 of the first significant DSM noise peak, or the shaped quantization noise leaks through as phase noise on the output. Higher-order DSMs push noise further out, letting you widen the loop bandwidth for faster lock — at the cost of more digital area and potential limit cycles that need LSB dithering to break.

Real use: every cellular radio (LTE, 5G) uses fractional-N to hop channels on kHz grids from a single ~26 MHz crystal. Modern CPUs use it for per-core DVFS — each core's PLL can independently hit any frequency in ~10 MHz steps without switching references.