Every OS scheduler needs to answer one question: "Wake me up at time T." The Local APIC timer is the hardware that answers it. But how it answers changed dramatically around 2010, and understanding that change explains why modern Linux tickless kernels are even possible.

The old way: periodic and one-shot mode. The classic Local APIC timer is a 32-bit down-counter clocked by the bus (or a divided version of it). You write an initial count, and it decrements every tick. When it hits zero, it fires an interrupt. In periodic mode it auto-reloads; in one-shot mode it stops. Simple, but two problems bite hard:

• Resolution is bus-clock dependent. If the bus runs at 100 MHz and you want a 3.7 µs wakeup, you compute ticks = 370. Fine — but the bus clock isn't constant across sleep states, and the OS has to recalibrate constantly.
• Reprogramming is expensive. Writing the initial count register is an MMIO write to the APIC, which serializes and costs dozens of cycles. On a tickless kernel, every idle-to-wake transition touches this register.

TSC-Deadline mode (Intel, Nehalem-era, 2010). Instead of a countdown, you write a 64-bit absolute deadline to IA32_TSC_DEADLINE_MSR, expressed in TSC ticks. The APIC compares the TSC against your deadline every cycle; when TSC ≥ deadline, it fires. Writing zero disarms it.

Why this matters:

• Nanosecond resolution. TSC runs at the invariant CPU base frequency — typically 2-3 GHz. One tick ≈ 0.3-0.5 ns.
• No conversion. The scheduler already tracks time in TSC ticks. It writes current_tsc + delta. No divide, no calibration.
• MSR write, not MMIO. WRMSR to the deadline register is ~20-30 cycles vs. ~100+ for an APIC MMIO write.
• No wraparound bugs. The 32-bit counter maxed out at ~40 seconds on a 100 MHz bus. TSC-deadline is 64-bit — good for ~200 years at 3 GHz.

Concrete example. Linux's clockevents subsystem prefers TSC-deadline when available (grep tsc_deadline_timer /proc/cpuinfo). When a task sleeps for 500 µs on a 3 GHz CPU, the kernel computes rdtsc() + 1_500_000 and issues one WRMSR. That's it. Compare this to the old periodic 1000 Hz tick, which fired every millisecond whether needed or not — a modern idle laptop core can now go tens of milliseconds between interrupts.

Rule of thumb: if your workload has many short sleeps (network stacks, high-frequency timers, real-time audio), the deadline mode saves you roughly 50-80 cycles per timer arm vs. legacy mode. Multiply by wakeups/sec and you find real single-digit-percent CPU savings on idle-heavy systems.