Current-mode control is the dominant architecture in modern switching regulators because it gives you inherent cycle-by-cycle current limiting, simpler compensation, and excellent line rejection. But there's a nasty artifact hiding in every current-mode controller that will drive you mad if you don't know about it: the turn-on current spike. Leading-edge blanking (LEB) is the elegant fix.

The problem: When the main MOSFET turns on, a huge current spike flows through the sense resistor for the first 50–200 ns. This spike isn't real inductor current — it comes from three sources: (1) reverse recovery of the freewheeling diode dumping charge through the FET, (2) discharge of the FET's own Coss and the switch-node parasitic capacitance, and (3) gate-charge injection through Cgd. On a 100 mΩ shunt, a 5 A spike looks like 500 mV — enough to trip the current-limit comparator and terminate the pulse instantly, causing pulse-skipping, subharmonic oscillation, or complete failure to start.

The fix: Blank (ignore) the current-sense comparator for a fixed window right after the gate drive goes high. Inside the IC, this is usually a one-shot triggered by the PWM latch's set pulse that disables the current comparator's output for tBLANK. After the window expires, the comparator sees the real, smoothly ramping inductor current.

Design rule of thumb: Set the blanking time to roughly 3× the sum of the FET turn-on time plus the diode reverse recovery time (trr). For a typical 500 kHz buck with a Schottky freewheeling diode (trr ≈ 10 ns) and a FET with 30 ns turn-on, you want tBLANK ≈ 100–150 ns. Most integrated controllers fix this internally (LT3690: 65 ns; LM3478: 125 ns), but discrete UC3843-style designs let you tune it with an external RC filter on the sense pin.

Real-world example: You're designing a 12 V-to-5 V, 3 A buck with a UCC28C43 running at 300 kHz and a 33 mΩ shunt. Without LEB, the 8 A turn-on spike creates 264 mV across the shunt — well above the 1 V current-limit threshold divided by your sense gain. The regulator refuses to start under load. Add an RC filter (100 Ω + 470 pF, τ = 47 ns) between the shunt and the ISENSE pin. This adds external blanking on top of the IC's internal ~100 ns, cleanly suppressing the spike while still catching real overcurrent within one switching cycle.

Watch out: Blanking too long defeats the purpose of cycle-by-cycle protection — a hard short might destroy the FET before the comparator ever gets to look at the current. Keep tBLANK under 15% of the minimum on-time.