When you apply power to a digital system, nothing is guaranteed. Supply voltage ramps up over milliseconds, oscillators need time to stabilize, and flip-flops wake up in random states. Without a power-on reset (POR) circuit, your state machines start in garbage states and your registers hold nonsense. The system must hold everything in reset until conditions are safe for operation.

The simplest POR circuit is an RC delay. A resistor and capacitor form a time constant: when power is applied, the capacitor charges slowly through the resistor. A Schmitt trigger inverter watches this rising voltage. While the cap voltage is below the trigger threshold, the output holds the system in reset. Once it crosses the threshold, reset deasserts and the system starts.

The math is straightforward. The RC time constant τ = R × C. The voltage reaches about 63% of VDD after one τ, and 95% after 3τ. If your oscillator needs 5ms to stabilize, you want your reset to hold for at least 10ms (2× margin). With a 100kΩ resistor: C = τ/R = 10ms / 100kΩ = 100nF. That's a real design calculation you'd do on a datasheet.

Why not just use software? Because the processor itself needs reset. The program counter, stack pointer, and peripheral configuration registers all need defined initial states before any instruction can execute. This is a chicken-and-egg problem that only hardware can solve.

Modern microcontrollers include integrated POR circuits that monitor supply voltage with precision comparators. These typically watch for VDD to cross a defined threshold (e.g., 1.8V on a 3.3V rail) and hold reset for a fixed number of internal oscillator cycles after that. Many also include brownout detection (BOD) — if VDD dips below a safe operating voltage during runtime, the chip resets itself rather than risk corrupted execution.

In FPGA designs, the story is more complex. Xilinx and Intel FPGAs have dedicated global set/reset (GSR) networks that initialize all flip-flops during configuration. But after configuration completes, your design needs its own reset strategy. Best practice is a synchronous reset: take the asynchronous POR signal, pass it through a two-stage synchronizer (two flip-flops in series, just like clock domain crossing), and distribute the synchronized version. This prevents reset deassertion from violating setup/hold times.

A real-world gotcha: reset sequencing. In systems with multiple supply rails (1.2V core, 3.3V I/O, 1.8V memory), powering them up in the wrong order can forward-bias internal ESD diodes and damage the chip. Power management ICs (PMICs) enforce sequencing, and the POR signal should not deassert until all rails are stable.