Wide vector instructions don't come free. When a core executes AVX-512 (and to a lesser extent AVX2) instructions, it activates a much larger swath of silicon — 512-bit ALUs, wider data paths, and additional FMA units. That silicon draws more current than the chip's voltage regulators can sustain at peak turbo frequency, so the CPU downclocks the offending core (and on older Skylake/Cascade Lake, the entire socket) to stay within its power and thermal envelope.

Intel divides instructions into three "license levels":

• License 0: scalar and light 128/256-bit code — full turbo.
• License 1: heavy 256-bit (AVX2 FMA) or light 512-bit — moderate downclock (~200–400 MHz).
• License 2: heavy 512-bit (AVX-512 FMA) — aggressive downclock, sometimes 30–40% off base.

The transition isn't instant. The core enters the lower license immediately upon executing a qualifying instruction, but it stays in that license for roughly 2 milliseconds after the last one — a hysteresis window so the voltage rail doesn't oscillate. So a single stray AVX-512 instruction in a tight scalar loop can crater throughput for millions of cycles afterward.

Real-world example: glibc's memcpy on Skylake-X used AVX-512 for large copies. A web server doing one big memcpy per request would knock the core into License 2; subsequent scalar request-parsing code ran at 2.4 GHz instead of 3.5 GHz until the 2 ms window expired. Cloudflare measured this in production and disabled AVX-512 in their build — the scalar penalty on hot paths outweighed the vectorized memcpy win. The same issue bit numpy users who saw single-threaded scripts get slower after upgrading to AVX-512-enabled BLAS.

Rule of thumb: AVX-512 pays off only when the vectorized region runs for at least ~20 µs of continuous SIMD work. Below that, the frequency penalty during the surrounding scalar code (lasting 2 ms) dwarfs the speedup. Compute the breakeven: if vectorization is 3× faster but the core runs at 0.75× frequency for 2 ms afterward, you need ~500 µs of scalar work after the SIMD region to break even.

Ice Lake and newer chips reduced the penalty dramatically — per-core voltage domains mean one core's AVX-512 no longer drags down its neighbors, and the downclock magnitude shrank. Sapphire Rapids made the License 2 penalty nearly negligible. But you still need to cat /proc/cpuinfo | grep avx512 and check the microarchitecture before assuming wide vectors are a win.