When your CPU writes 8 bytes to memory, then 8 more, then 8 more — sending each one as a separate transaction across the memory bus is catastrophically wasteful. DRAM is optimized for burst transfers (typically 64 bytes — one cache line), not for 8-byte dribbles. The bus protocol overhead (address phase, command phase, turnaround) can be larger than the data payload itself. A write-combining buffer (WCB) is hardware that sits between the CPU and memory, catches small adjacent stores, and merges them into one cache-line-sized burst before sending them out.

Structurally, a WCB is a small set of fully-associative entries (Intel CPUs have ~10 of them, called "fill buffers"), each holding one cache line's worth of data plus a byte-valid bitmask. When a store arrives:

• Hardware checks if any existing buffer entry matches the store's cache-line address.
• Hit: merge the new bytes into that entry, set the valid bits, done — no bus traffic.
• Miss: allocate a fresh entry, store the bytes, mark their valid bits.
• The entry stays open, accumulating more stores, until it's evicted: either it fills up completely (all 64 bytes valid → optimal burst), gets old (timeout), or a serializing instruction like SFENCE forces a flush.

Real example: writing to a graphics framebuffer mapped as write-combining memory (Intel's WC memory type, set via MTRR or PAT). The GPU's BAR is across the PCIe bus — every transaction has ~100ns of overhead. Without WC, drawing a horizontal line of 64 pixels (256 bytes) issues 64 separate 4-byte PCIe writes — 6400ns of overhead. With WC, hardware merges them into four 64-byte bursts — 400ns of overhead. That's a 16× speedup on pixel-pushing code, with zero software changes beyond the memory type setting.

The catch — ordering: WC stores are weakly ordered. If your code writes a command buffer then rings a doorbell register, the doorbell might arrive before the command bytes are flushed. The fix is an SFENCE between them, which evicts all WCB entries before letting the doorbell store proceed.

Rule of thumb: if your store stream's combining efficiency (valid bytes per evicted line ÷ 64) drops below ~50%, you're paying more bus overhead than you're saving. Strided writes (e.g., writing every 4th byte) defeat WCBs because each store opens a new entry, evicting an older partially-full one. Always write contiguously when possible — sequential stores hit the same entry and combine perfectly.

Modern CPUs also use WCBs internally for non-temporal stores (MOVNTQ, MOVNTDQ), which bypass the cache entirely and dump straight to memory through the WCB — ideal for streaming writes that you'll never read back.