The classic 6T SRAM cell (two cross-coupled inverters + two access transistors) has a dirty secret: reading and writing fight each other. During a read, the bit-lines are precharged high and the access transistors pull the internal "0" node upward through a voltage divider with the pull-down NMOS. If that node rises above the trip point of the opposite inverter, the cell flips — a read destroys the data. This is called read disturb, and it's why 6T sizing obsesses over the cell ratio (pull-down strength ÷ access strength, typically ≥1.8).

At nominal voltage (say 0.9V) the margin is thin but workable. At near-threshold voltages (0.4–0.5V, where modern low-power chips want to run), transistor variability (σVt) becomes a huge fraction of the supply. The read-disturb margin collapses, and cells start flipping randomly. You cannot scale a 6T cell below about 0.7V reliably.

The 8T cell fixes this by adding a dedicated read port: two extra NMOS transistors form a read buffer that senses the storage node but never drives it. The write path still uses the two original access transistors on differential bit-lines (BL/BLB), but the read path uses a single-ended read bit-line (RBL) and a separate read word-line (RWL). Because the read buffer's gate connects to the storage node (infinite input impedance), reading cannot disturb the cell. You can now operate down to ~0.5V.

The 10T cell goes further: it adds two more transistors to fully isolate the read stack from VDD leakage during standby, and to allow differential read at ultra-low voltage. Intel's near-threshold research chips and IoT-class MCUs use 10T for their L1 caches when they need to run at 0.35V.

Concrete example: ARM's Cortex-M33 low-power caches and Intel's Claremont near-threshold Pentium prototype used 8T bit-cells to reach sub-500mV operation, cutting cache leakage by 10× versus 6T at the same voltage.

The cost:

• 8T: ~30% larger cell area than 6T (2 extra transistors, extra RWL and RBL routing).
• 10T: ~60% larger, plus more wire tracks per row.
• Density hit is real — this is why 8T/10T shows up in L1 and register files, but L2/L3 stays 6T where you can afford ECC and voltage margining instead.

Rule of thumb: if your minimum operating voltage (Vmin) target is below 0.7V, budget for 8T. Below 0.5V, budget for 10T. Above 0.7V, stick with 6T and spend the area on more cache.