A flash ADC (also called a parallel ADC) is the fastest analog-to-digital converter topology ever built. It converts a voltage to an N-bit digital code in one clock cycle by throwing brute-force parallelism at the problem: it uses 2^N − 1 comparators firing simultaneously against a resistor ladder of reference voltages.

How it works. A precision resistor string divides the reference voltage into 2^N equal steps. Each tap connects to the negative input of one comparator; every comparator's positive input receives the analog signal in parallel. Comparators below the input voltage output '1'; those above output '0'. The result is a thermometer code — a stack of 1s below a boundary and 0s above (e.g., 00011111). A priority encoder or thermometer-to-binary decoder collapses this into an N-bit binary word in one more gate delay.

The exponential cost. This is the defining tradeoff. Every extra bit doubles the comparator count:

• 4-bit flash: 15 comparators
• 6-bit flash: 63 comparators
• 8-bit flash: 255 comparators
• 10-bit flash: 1,023 comparators — power, area, and input capacitance become prohibitive

Rule of thumb: flash ADCs are practical up to about 6–8 bits. Beyond that, use a folding, pipelined, or subranging architecture that reuses comparators across multiple clock phases.

Real-world example: high-speed oscilloscopes and serial link receivers. A Keysight Infiniium 110 GHz scope's front-end samples at 256 GS/s using flash ADCs (typically 8-bit) interleaved across many channels. The input signal drives 255 comparators in parallel — the entire conversion completes in the propagation delay of one comparator plus the encoder, roughly 10–20 ps in a modern SiGe or 7nm CMOS process. Similarly, 112 Gb/s PAM-4 SerDes receivers use 3-bit flash slicers (7 comparators) inside each ADC-based DSP receiver to digitize symbols at 56 GBaud.

Watch out for these gotchas:

• Comparator offset mismatch — each comparator has ~5–20 mV of random input-referred offset. For an 8-bit ADC with a 1 V reference, one LSB is only ~4 mV, so offset calibration or auto-zeroing per comparator is mandatory.
• Bubbles in the thermometer code — a noisy comparator near the boundary may flip out of order (00011011), producing wrong binary output. Use 1-of-N encoders or majority voting to suppress bubbles.
• Massive input capacitance — 255 comparator gates in parallel present a huge load to whatever drives the analog input, requiring a strong buffer or T&H amplifier.