A clock recovered from a backplane, a SerDes lane, or even a stratum-3 telecom line arrives functionally correct but spectrally filthy. Its edges wander in the picosecond range due to power supply noise, channel ISI, and reference imperfections. Feed that clock to a high-speed DAC or a 10G transmitter and your output spectrum smears, your BER explodes, and your SNR collapses by 10+ dB. The fix isn't a better oscillator — it's a jitter cleaner: a cascaded PLL specifically designed as a low-pass filter on phase noise.

The trick is exploiting the PLL's transfer function. A PLL has a jitter transfer bandwidth — input phase noise below this frequency passes through, noise above it gets attenuated by the loop filter at 20 dB/decade. So if your dirty input clock has jitter centered at 1 MHz, you build a PLL with a loop bandwidth of 100 Hz, and that 1 MHz jitter gets attenuated by 80 dB. The output tracks only the long-term average of the input.

But there's a catch: a narrow loop bandwidth means the VCO runs nearly free, so you need a VCXO (voltage-controlled crystal oscillator) with intrinsically low phase noise — typically <100 fs RMS integrated jitter. The crystal provides the short-term stability; the PLL provides the long-term lock.

Real-world example: The Texas Instruments LMK04828 is a workhorse jitter cleaner used in 5G basestations and high-speed ADC clocking. It accepts a sloppy 122.88 MHz reference (perhaps recovered from a SyncE Ethernet link with ~10 ps RMS jitter), locks a 100 Hz-bandwidth PLL to it driving a VCXO, then cascades into a second wider-bandwidth PLL that multiplies up to 3 GHz with multiple low-jitter LVPECL outputs. Total output jitter: under 100 fs RMS, integrated 12 kHz–20 MHz. That's good enough for a 16-bit ADC at 500 MSPS.

Rule of thumb: Jitter attenuation in dB above the loop bandwidth ≈ 20·log10(f_jitter / f_loop). So a 100 Hz loop attenuates 10 kHz jitter by 40 dB, 100 kHz jitter by 60 dB. But: noise at the loop bandwidth gets peaked by 1–3 dB from loop dynamics, so always design the bandwidth to sit in a quiet region of your input's noise spectrum.

Cascaded PLLs solve a second problem: frequency translation. Stage 1 cleans and locks; stage 2 multiplies to a non-integer ratio using fractional-N. Splitting these jobs across two loops lets you optimize bandwidth independently for each — narrow for cleaning, wider for fast frequency settling.