2026-07-25
Peak current-mode control is beloved for its cycle-by-cycle overcurrent protection and inherent input feedforward. But it has one nasty habit: sub-harmonic oscillation at duty cycles above 50%. The fix is a technique called slope compensation, and every current-mode controller IC you'll ever touch implements some version of it.
Why it happens: In peak current-mode, the switch turns off when the inductor current ramp hits the error amplifier's command level. Any perturbation to the peak — a bit of noise, a load step — shifts where the next cycle starts. If the down-slope (m₂) of the inductor current is steeper than the up-slope (m₁), the perturbation shrinks each cycle and dies. If m₂ < m₁ (which happens when D > 0.5), the perturbation grows each cycle, alternating between wide and narrow pulses. You'll see it on a scope as a period-doubled waveform at half the switching frequency.
The fix: Add an artificial ramp (slope m_c) to the sensed current signal before it hits the comparator. The stability criterion becomes:
Concrete example: A buck converter with Vin = 24 V, Vout = 15 V (D = 0.625, well above 0.5), L = 22 µH, fsw = 500 kHz, and a current-sense gain of 0.1 V/A.
Over one switching period (2 µs), that's a ramp of roughly 68–136 mV added to the sense signal. Most controllers (LM5116, UCC28C43, LT3845) either build this in or expose a pin where you inject the ramp from the oscillator through a resistor.
Side effects to watch: too much slope compensation pushes you toward voltage-mode behavior — you lose the input feedforward benefit and the loop's low-frequency gain drops. The current limit also becomes duty-cycle-dependent (peak limit sags at high D), which is why datasheets specify current limit at a specific D.
If you ever build an SMPS from discrete parts and see the switching waveform "breathing" between fat and skinny pulses at half your clock rate — that's insufficient slope comp, not a bad MOSFET.