DRAM sense amplifiers read tiny voltage differences — often 100 mV or less — between a bit-line and its reference. But bit-lines run in parallel for millimeters through a memory array, and adjacent bit-lines couple capacitively. If a neighboring bit-line swings the wrong direction at the wrong moment, its coupling pulls your signal below the sense amp's threshold, and you read the wrong bit. Bit-line twisting is the geometric trick that cancels this coupling without adding any transistors.

The core idea: swap the physical positions of the true and complement bit-lines (BL and BL̄) partway down the array, so each line spends half its length adjacent to one neighbor and half adjacent to the other. Any capacitive coupling from a neighboring column now injects charge onto BL and BL̄ equally — and since the sense amp reads the difference, the common-mode noise cancels.

Three common patterns:

• Open bit-line: No twisting. Simple, but adjacent-column coupling directly attacks the differential signal. Only viable at older nodes.
• Folded bit-line with one twist: BL and BL̄ swap once at the array midpoint. Cancels first-order coupling to the two adjacent columns.
• Triple-twisted (Samsung's 3-twist scheme): Three crossovers at 1/4, 1/2, and 3/4 down the array. Cancels coupling from both immediate neighbors and second-nearest neighbors — essential below 20 nm where every neighbor matters.

The rule of thumb: Coupling noise scales as C_c / (C_c + C_bl), where C_c is the sidewall capacitance between adjacent bit-lines and C_bl is the total bit-line capacitance to ground. At advanced nodes, C_c can reach 40% of C_bl. Without twisting, a single aggressor swing of 1V injects ~400 mV onto its neighbor — four times the sense margin. One twist cuts that to a few tens of millivolts of residual (from imperfect matching); three twists cut it below 10 mV.

Real-world example: Micron's LPDDR5 dies at 1α-nm use a variant of triple-twisted bit-lines specifically because the wordline pitch dropped below the point where a single twist left too much residual coupling from the second-nearest column. The twist adds zero silicon area — it's implemented purely in the metal routing layer as a small keep-out region where BL and BL̄ cross via short jogs on an upper metal.

The catch: each twist point requires a via-jog-via structure, which adds resistance and a small capacitive discontinuity. Too many twists and the bit-line RC delay eats your row-access time. Modern DRAM designers pick the minimum number of twists that meets the sense-margin budget — usually one or three, rarely more.