2026-07-07
Every flip-flop you've seen so far samples on one edge — rising or falling. If you want to move data twice per clock cycle, the obvious answer is to double the clock frequency. But doubling the clock doubles the dynamic power (P ∝ fCV²) and forces the clock tree to meet timing at 2× the rate. The clever alternative: a dual-edge-triggered flip-flop (DETFF) that captures on both the rising and falling edges of the original clock.
The naive DETFF puts two D flip-flops in parallel — one rising-edge, one falling-edge — and multiplexes their outputs based on clock polarity. It works but costs roughly 2× the area and 2× the clock load, which erases most of the power savings. The interesting DETFFs share transistors between the two paths.
The classic latch-mux DETFF uses two transparent latches (one on CLK-high, one on CLK-low) whose outputs feed a 2:1 mux selected by CLK itself. When CLK is high, the low-latch is holding a value it captured on the last falling edge, and the mux forwards it. When CLK falls, the high-latch takes over. The result: Q updates on every clock edge, but each individual latch and its clock-gated data path only switches at the original frequency.
Where you actually see this:
Rule of thumb: A well-designed DETFF costs about 1.4× the area of a single-edge FF but saves about 40–45% of clock-tree power at equivalent throughput. The break-even hits when the clock tree accounts for more than ~30% of total dynamic power, which is common in modern chips (clock trees routinely eat 20–40% of the dynamic power budget).
The catch nobody mentions: DETFFs have two setup/hold windows per cycle instead of one, so your timing analyzer has to check both edges independently. Duty-cycle distortion of the clock now directly steals from your timing margin — a 48/52 duty cycle that a single-edge FF ignores completely will burn 40 ps of margin in a DETFF at 1 GHz. This is why DETFFs almost always come paired with duty-cycle correction circuits upstream.