Every IC on your board is a tiny, demanding load that draws sharp current spikes — especially digital chips switching millions of gates. The power supply is connected through traces that have inductance, so it can't respond instantly. Decoupling capacitors act as local energy reservoirs, sitting right next to the IC and supplying those fast transient currents before the bulk supply even notices.

Without proper decoupling, you get voltage droops on the power rail that cause erratic behavior: logic glitches, ADC noise, oscillator jitter, and op-amps doing things you didn't design them to do.

The practical rules:

• Place a 100 nF (0.1 µF) ceramic capacitor as close as physically possible to each IC's VCC/GND pin pair. This is non-negotiable — it's the single most important layout habit you can build.
• Add a bulk capacitor (10 µF to 100 µF, electrolytic or ceramic) near the power entry point of each board section. This handles slower, larger current demands.
• For high-speed or noise-sensitive ICs (ADCs, PLLs, precision references), add a second smaller cap — 10 nF or even 1 nF — in parallel to extend the high-frequency decoupling range.
• Connect decoupling caps to the ground plane with short, wide traces or, ideally, vias directly to an inner ground plane. Long traces add inductance and defeat the purpose.

Why multiple values? A real capacitor has parasitic inductance (ESL) that creates a self-resonant frequency. Above that frequency, it stops behaving like a capacitor. A 100 nF 0805 ceramic typically self-resonates around 20–30 MHz. A 1 nF 0402 resonates up near 500 MHz. Using multiple values in parallel gives you low impedance across a wider frequency range.

A concrete example: Suppose you're designing a board with an STM32 microcontroller. The datasheet recommends 100 nF on each VDD pin and a 4.7 µF bulk cap. The STM32F4 has five VDD pins — that's five 100 nF caps, each placed within 2–3 mm of its respective pin, plus one 4.7 µF near the power connector. Skip these and you'll spend days debugging mysterious resets and corrupted SPI transfers.

Quick impedance calculation: The impedance of a capacitor at a given frequency is Z = 1 / (2πfC). At 1 MHz, a 100 nF cap presents about 1.6 Ω. At 10 MHz, it drops to 0.16 Ω. That low impedance is what shunts high-frequency noise to ground and keeps your power rail clean.

One last tip: a ground plane is not optional. It's the return path for all those fast currents. A fragmented or missing ground plane will undermine even perfect capacitor placement.