Power gating shuts off a whole block by inserting a header or footer transistor between the logic and the rail. But cutting the rail entirely means losing state, paying wake-up latency, and dealing with rush current. Stack forcing is the lighter-weight cousin: instead of disconnecting the rail, you exploit the fact that two off-transistors in series leak far less than one.

The physics: leakage current through an off NMOS is exponential in V_GS minus V_th. When you stack two NMOS devices and turn both off, the intermediate node floats up to some voltage V_x > 0. That means the top transistor sees a negative V_GS (its source is V_x, its gate is 0), and its V_DS is reduced. Both effects (negative gate bias and DIBL reduction) cut leakage. The result: a stack of two off devices leaks roughly 5–10× less than a single off device of the same total width.

The rule of thumb: doubling the stack height typically cuts subthreshold leakage by ~1 order of magnitude in modern bulk CMOS, at the cost of ~20–30% slower switching when active (because now you're driving two series devices).

Concrete example — an idle ALU in a mobile SoC: A 64-bit adder built with single-transistor pull-down networks might leak 50 µA at 0.9V and 85°C. Refactor the same logic so every pull-down path has a stacked transistor pair (often achievable by duplicating a control signal as the "enable" device), and the leakage drops to ~6 µA. Across a chip with thousands of such gates idle most of the time, that's the difference between 8 hours and 12 hours of standby battery life.

Where this beats classical power gating:

• No state loss — flip-flops keep their values because the rail never goes away.
• Zero wake-up latency — the block is always "ready," just slow when leaking-optimized paths are exercised.
• No header/footer sizing problem — you don't need a giant sleep transistor sized to carry peak active current.

Where it loses: the leakage reduction is ~10×, not the ~1000× you get from a real power gate cutting the rail. So stack forcing is for blocks that are often idle but occasionally needed quickly — branch predictors, victim caches, debug logic — while full power gating remains the tool for blocks that are idle for milliseconds at a time.

Synthesis tools can apply stack forcing automatically by recognizing parallel pull-down networks and serializing them when timing slack allows, often as part of a "leakage recovery" pass after place-and-route.