For decades, CPU caches lived on the same silicon die as the cores, competing for area with everything else. 3D V-Cache (AMD's marketing name; the technique is hybrid bonding or TSV stacking) breaks that constraint by bonding a second silicon die directly on top of the CCD, tripling L3 capacity without touching the core layout.

The trick: through-silicon vias (TSVs) punch vertical connections through the base die to a cache-only die stacked above. AMD's implementation uses direct copper-to-copper hybrid bonding (no solder bumps), giving inter-die bandwidth similar to on-die wires. The stacked SRAM die adds 64MB of L3 on top of the 32MB base, yielding 96MB total per CCD.

Why stacking, not just a bigger die?

• Wafer yield: SRAM has huge, regular structures — much higher yield per mm² than logic. Fabricating cache separately on an optimized process avoids dragging down CPU yield.
• Wire length: A 96MB planar L3 would require signals to traverse a much larger die area, adding latency. Vertical stacking keeps wires short.
• Thermal reality: SRAM sits above the cores — but SRAM generates almost no heat compared to logic. It insulates the hot cores from the heatspreader, forcing AMD to lower peak clock speeds on X3D parts by ~200-400 MHz.

Real-world impact: The 7800X3D beats the 7700X in gaming by 15-30% despite lower clocks, because game code often has a working set that fits in 96MB but not 32MB. Factorio's late-game simulation improves ~70%. Meanwhile, compilation workloads (which stream through memory rather than reuse hot data) gain almost nothing and lose to the non-X3D chip because of the clock deficit.

Rule of thumb: If your working set W satisfies 32MB < W < 96MB and access patterns show temporal reuse, expect V-Cache speedups of 15-40%. If W < 32MB (fits in base L3) or W >> 96MB (streams through both), expect zero benefit and a small clock-driven regression.

Latency cost: The stacked L3 adds ~4 cycles vs. the base L3 (from ~46 to ~50 cycles on Zen 4), because addresses must be hashed across a larger slice count and signals traverse TSVs. AMD hides this by keeping the base 32MB as the "fast" region for hot data, essentially creating an L3.5.

Intel's competing approach — Foveros — stacks logic-on-logic (used in Meteor Lake's compute tile atop the base tile), a harder thermal problem but more flexible than cache-only stacking.