When a software engineer imports a library, the compiler figures out how it fits. When a hardware engineer imports an IP block — say, a USB PHY, a PCIe controller, or a DDR4 memory interface — the block arrives pre-placed, pre-routed, pre-timed, and pre-characterized for a specific process node. That process is called hardening, and it's the reason a $2M PCIe Gen5 controller license is cheaper than designing one yourself.

A soft IP is delivered as synthesizable RTL (Verilog/VHDL). You get flexibility — retarget to any process, tune parameters, integrate freely — but you also inherit all the risk: synthesis, place-and-route, timing closure, and silicon verification are on you. A hard IP is delivered as a GDSII layout: transistors, wires, and vias frozen in geometry, characterized on a specific foundry process (e.g., TSMC N5). You get guaranteed timing and area, but zero flexibility — it's a black box with fixed pinout and power ports.

Firm IP sits in between: gate-level netlist plus placement guidance, letting the integrator do final routing.

Hardening a block involves:

• Floorplan lock: pin locations, power ring, block aspect ratio all fixed
• Clock tree synthesis tuned to a specific insertion delay budget
• Timing signoff across all PVT corners with signed .lib files
• Abstract views: LEF (physical footprint), Liberty (timing/power), GDSII (mask data), and encrypted Verilog for simulation
• DRC/LVS clean against the target foundry's design rules

Real-world example: Synopsys DesignWare USB 3.2 PHY is delivered as a hard macro for TSMC N7. It's a ~1.5mm² rectangle with fixed pin locations on all four sides, characterized across -40°C to 125°C and 0.72V–0.88V core supply. You drop it into your floorplan, connect the digital ports, route the analog reference pins per the integration guide, and it just works. Apple, Qualcomm, and Nvidia all license the same PHY — the silicon is proven across thousands of tapeouts, which is why nobody rolls their own.

Rule of thumb: If a block requires analog design, uses more than ~50k gates of tightly-timed logic, or must hit a standardized interface spec (PCIe, USB, DDR, Ethernet SerDes), license hard IP. The NRE savings versus in-house design typically pay back the license fee within one tapeout — plus you avoid a 6-month schedule slip when your custom PLL fails at hot-slow corner.

The trade-off: hard IP locks you to one foundry and one node. Porting to a new process means relicensing (and often a 12+ month wait while the vendor re-hardens).