Building a RISC-V Soft Processor on Lattice ECP5 FPGA Colorlight 5A-75E with Propel Builder

2026-08-26

Building a RISC-V Soft Processor on Lattice ECP5 FPGA Colorlight 5A-75E with Propel Builder

Channel: Muhammad Yunus (3540 subscribers)

This project hits a sweet spot for anyone curious about FPGAs, soft processors, or hardware hacking on a budget. The Colorlight 5A-75E is a cheap LED matrix receiver card (typically under $20 on the used market) built around a Lattice ECP5 25F FPGA — a chip well-known in the open-source FPGA community because it's fully supported by the Yosys/nextpnr toolchain. Repurposing these boards has become a rite of passage for FPGA hobbyists.

What makes this video worth watching is the specific workflow: instead of using the open-source toolchain, the creator uses Propel Builder (Lattice's official IDE) to synthesize a RISC-V soft processor onto the fabric. That means walking through IP integration, memory mapping, clock configuration, and finally programming the bitstream onto a board that was never intended to run a CPU. The result is a working RISC-V core on hardware that costs less than a nice lunch.

For viewers, the value is threefold: you learn how to salvage cheap production hardware for custom compute, you see the vendor-supported RISC-V flow (useful context even if you prefer open tools), and you get a concrete example of soft-core CPU deployment on real silicon.

Why watch: A practical walkthrough of turning a $20 LED controller into a working RISC-V computer using Lattice's official FPGA toolchain.

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