Every high-speed ADC, SerDes receiver, and SRAM sense amp needs to answer one question millions of times per second: is voltage A greater than voltage B? A linear op-amp comparator burns static current and is slow. The StrongARM latch (originally called the Kobayashi latch, popularized in the DEC StrongARM CPU in 1996) does it in ~50 picoseconds with zero static current. It's arguably the most-copied circuit in modern mixed-signal design.

The topology has three phases driven by a clock:

• Reset (clock low): PMOS switches precharge both output nodes and both internal drain nodes to VDD. The tail NMOS is off, so no current flows.
• Sampling (clock rising): Tail NMOS turns on. A differential input pair (M1/M2) begins discharging the two output nodes at rates proportional to Vin+ and Vin−. Whichever input is higher discharges its side faster.
• Regeneration: Once the output nodes fall below VDD−|Vtp|, a cross-coupled inverter pair (back-to-back PMOS+NMOS) kicks in. This positive-feedback latch amplifies the tiny voltage difference exponentially: ΔV(t) = ΔV₀ · e^(t/τ), where τ ≈ Cload/gm. Within one time constant, the winning side snaps to VDD and the loser to GND.

The key insight: the input pair only needs to create a tiny voltage imbalance (~10 mV) before regeneration takes over. That's why StrongARM latches can resolve millivolt-scale inputs in tens of picoseconds without amplification — you're not amplifying, you're tipping a metastable node the right direction.

Real-world example: A 12-bit, 1 GS/s pipelined ADC uses ~24 StrongARM comparators per stage (one per 1.5-bit sub-ADC). At 1 GHz, each comparator resolves a decision in under 500 ps and dissipates only dynamic energy (CV²f). If you tried this with static op-amps, you'd burn ~100× the power and never hit the speed.

Rule of thumb: The regeneration time to resolve ΔV₀ into a full logic swing VDD is t_reg ≈ τ · ln(VDD/ΔV₀). For τ = 5 ps, VDD = 1.0 V, and a 10 mV input: t_reg ≈ 5 · ln(100) ≈ 23 ps. Halve the input and you only add τ·ln(2) ≈ 3.5 ps — logarithmic scaling is the entire point.

The catch: if the input difference is below the latch's offset voltage (typically 5–20 mV due to threshold mismatch), the decision becomes random — this is metastability, same as any flip-flop. Designers add offset-cancellation phases or use larger input transistors (offset scales as 1/√WL) to trade area for resolution.